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[QUOTE=Guest;171590]JYOTHSNA KASIRALLA
 
[b]E-Mail [/b]: josh.jyothsna9 AT gmail.com 
4 years of experience in embedded testing with specialization in the area of Requirement based testing, Module testing, White box testing, Functional Verification Testing, Model based testing , Regression Testing and Verification and Validation in Avionics domain.
PROFESSIONAL PRÉCIS
- Well versed with Module/unit testing, Requirement Based Testing, Functional Verification Testing, Model based testing, regression testing, code reviews, FVT Reviews, HSIT Reviews & methodologies followed in Avionics Domain
- Deft in writing test cases, test scripts, test procedures and executing test scripts in Target
- Expertise in various software testing projects entailing creation and execution of manual test scripts in various tools.
- Strong abilities in Manual and Automation Testing involving setting up of test environment, creation of test scripts / cases, execution of component / functional / performance / system / regression tests and tracking of defects
- Having good exposure to Software Development Life Cycle and related process.
- Good knowledge of DO-178B for software development and verification in Avionics Domain.
- Expertise in Defect preventive Analysis and Project Quality Analysis
- Excellent communication, leadership and interpersonal skills with proven abilities in resolving complex software/ application related issues.
WORK EXPERIENCE
TENURE ORGANISATION DESIGNATION
Aug’10-tilldate Honeywell Technologies Solutions Lab Software Engineer 
 (Through Magna infotech)
Aug’06 -July’09 HCL Technologies at Bangalore Member Technical Staff
Jun’03-Aug’04 S.V.C.E.T, Chittoor Lecturer 
Areas of Expertise
Technical
[b]Languages  [/b]: C
[b]Operating Systems  [/b]: MS-DOS & Windows 98/2000/XP/VISTA/7 professional
[b]Packages  [/b]: MS Office 2000/XP & VHDL
[b]Assembly Languages  [/b]: 8085, 8086
[b]Tools  [/b]: Vector CAST 5.0, Clear Case, Clear Quest, TeamCenter Systems Engineering (TcSE), 
 Source Insight 3, Understand for C++, VC++, ARMS, Serena Dimensions (PVCS), 
 DOORS, PM Smart, JIRA tool, HiLite, CM21, MATLAB
[b]Structural Coverage Tool [/b]: RTRT
[b]Comparison tools  [/b]: Beyond Comparator, Ultra Edit 
PROJECTS EXECUTED
[b]Title  [/b]: Next Generation Flight Management System (NGFMS)
[b]Client  [/b]: Boeing 747 and G650
[b]Test Environment  [/b]: VectorCAST 
[b]Tool  [/b]: VectorCAST/C++5.0 
[b]Role  [/b]: Tester
[b]Team Size  [/b]: 50
[b]Duration  [/b]: Dec’10-till date
[b]Description  [/b]: FMS provides inputs for Autopilot. In the broad sense, it handles Flight Planning, 
Navigation, Performance and Aircraft Control Functions. The NG architecture is organized into layers, with each layer having a distinct purpose. The Architecture is defined to consist of five layers User Interface Layer, Application Service Layer, Support Services Layer, Framework Services Layer and Platform Services Layer. Layers can only reference those layers below it. No references to layers above are allowed. 
 In this project Unit Test Procedure is done. Unit testing is done in VectorCAST environment by creating environment with header files, object files and UUT (.h and .cpp) files for the concerned UTP. Common and Test specific Stub files are necessary for Linking and Compilation purposes. Scripts (test cases) are written in TST file and is imported into VectorCAST and check for the test case failures and checked for statement and Branch coverage as per DO-178B level B.
Accountabilities
- Requirement Based Testing and white box testing in VectorCAST tool
- Understand and analyze the requirement and the interfaces.
- Creating the environment in VectorCAST with stubs.
- Test cases are written in VectorCAST environment as per the requirement.
- Check for the failed test cases, analyze and SCR is raised if required.
- If statement and Branch coverage is not 100% then analysis is required for non coverage.
- Disposition is written for SCR and any issues for non coverage like protective code, null body etc.
- The artifacts are configured in Clear Case which is used as configuration controller and the corresponding Active Record is created in Clear Quest.
- Team center is the Requirement management tool used to fetch the low level Requirements.
- JIRA is the process tool used for the project.
[b]Title  [/b]: Model (component) Testing for Flight Control Electronics (Boeing 787)
[b]Client  [/b]: Boeing, USA.
[b]Test Environment  [/b]: HiLite Run in CTP environment and RTRT for Requirement & structural 
 Coverage 
[b]Tool  [/b]: Matlab, RTRT
[b]Role  [/b]: Tester.
[b]Team Size  [/b]: 60
[b]Duration  [/b]: Aug’10-Nov’11
[b]Description  [/b]: Flight Control Electronics consist of flight control surfaces aileron, Rudder and Elevator controls allow a pilot to adjust and control the aircraft’s flight altitude. Fly By Wire (FBW) is used in the Boeing 787.A fly-by-wire (FBW) system replaces manual flight control of an aircraft with an electronic interface. The movements of flight controls are converted to electronic signals transmitted by wires (hence the fly-by-wire term), and flight control computers determine how to move the actuators at each control surface to provide the expected response. Commands from the computers are also input without the pilot's knowledge to stabilize the aircraft and perform other tasks.
 In this project component is the model and each model is given to the HiLite tool which generates test cases and checks for requirement coverage and the generated test cases are run in the CTP and RTRT is used to check for structural coverage. If coverage is not 100% then analysis is done and manual test cases are written.
Accountabilities
- Understand and analyze the model and execute the model in HiLite run in Matlab.
- Generated test cases are run in CTP environment and creating images.
- RTRT is used to perform structural coverage analysis
- If the coverage is not 100% then analyze the errors and manual test cases are written. 
- CM21 is the configuration controller used for the artifacts.
- Black box testing is the methodology in this project
PROJECTS EXECUTED in HCL
[b]Title  [/b]: Auxiliary Power Unit Controller (Boeing 787)
Client : Hamilton Sundstrand, USA.
Test Environment : On APS 5000 APUC and using the functional verification scripts on the AGE 70077 ATE
Tool : Visual Basic, Understand for C++, ARMS, Serena Dimensions (PVCS), DOORS, PM Smart
Role : Tester.
Team Size : 80
Duration : Oct ’07 to June’09
Description : 
Auxiliary Power Unit (APU) - It is a Gas Turbine Engine which drives:
- A Load Compressor to supply compressed Air
- Environment control System
- To start Main Engine
- An AC generator to supply Electrical power for Aircraft Systems.
APUC controls, monitors and diagnoses all phases of the APU. Operates through the various valves, motors and sensors. The APUC is a component of the Auxiliary Power System 5000(APS 5000) for Boeing 787 aircraft.
Main Functions of APUC are:
- To keep the power unit rotation speed constant to maintain AC generator frequency
- To protect the power unit from over temperature
- To ensure a correct start of the power unit
- To provide a correct start sequence
- To control compressor load surge
- To ensure correct shutdown sequence.
- To monitor APU component operation
- To supply fault information for trouble shooting, engine trend monitoring and historical data retention.
Accountabilities
- Configuring the artifacts in PVCS
- Study and understanding hardware/software functional requirements(Black box testing)
- Developing functional test scripts, test cases and test procedures.
- Integrating ATE, System simulator and APS 5000 ECB.
- Running, debugging and generating test artifacts, problem reporting. 
- Performed Requirement Based Testing, Module Testing, Regression Testing and Reviews.
- Performed Code Review, Functional verification Test Review, System requirement Reviews, HSIT Reviews
- Capturing the defects in ARMS checklist which is compliance with DO-178B
- DOORS is the requirement management tool used for the project.
Title : Non Boundary Scan Diagnostics
Client : HCL Technologies, Chennai.
Environment : JTAG Tool, Microsoft Office.
Role : Tester and Project Quality Analyst (PQA).
Team Size : 7.
Duration : Nov’06–Aug’07.
Description : The objective of the project is to identify several Non Boundary Scan Devices and circuit boards already existed and increasing the test coverage of the boards. For this several Input/Output signals, Digital signals and discrete signals has been identified. We designed three different circuit boards to cover all these signals. The three boards are Input/Output board, Digital Board, Discrete Board. JTAG scripts have been written to test the interfaces like RS232, SPI, I2C, UART, PROM, RAM, EEPROM etc. Several circuit boards like ARINC, DIBCOMM have been tested and increased the test coverage. 
Accountabilities
- Performing the requirement study & analysis.
- Finding Non Boundary scan devices and dividing them according to the type.
- Writing scripts in JTAG tool and testing the interfaces.
- According to the requirements, designing the IO Board, Digital Board, Discrete Board 
- Testing the above developed boards by the scripts developed in JTAG tool.
- Responsible as Project Quality Analyst (PQA).
OTHER ACCOLADES
- Paper presented on “Congestion Control for IP based CDMA Radio Access Networks” which was selected and published in the National Conference – LTTC in 2006.This is the thesis submitted for my M.Tech project.
- Obtained 49th rank in 1998 - ECET examination - A.P. State.
- Stood one among the top 5 in M.Tech & B.Tech Examinations.
- Topped the school during class X examinations.
ACADEMIC CREDENTIALS
M.Tech. (Digital Systems and Computer Electronics)
J.N.T.U College of Engineering, Anantapur in 2006. Secured 77.5% marks.
B.Tech. (Electronics and Communication)
J.N.T.U College of Engineering, Hyderabad in 2002. Secured 76.33% marks.
CAREER INTEREST
Flexible to work in various Manual/Automation Tools, Black box testing, White box testing, Regression testing, Performance testing.[/QUOTE]

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