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[QUOTE=Guest-IJT;141394][b]Name [/b]: Mohini Vilasrao Somvanshi [b]Email [/b]: mohini.somvanshi AT gmail.som [b]Designation / Skillset[/b] : Cadence,VHDL,Verilog,Mentor Graphics [u][b]Resume[/b][/u] : [b]CARRER AIM [/b]: Be a part of goal oriented team in an organization, where my technical background interpersonal skills can lead to both, growth of company as well as my own carrier. [b]EDUCATION [/b]: 2011(pursuing) M.Sc (Electronic Science) – University of Pune - Specialization in VLSI Design - Current GPA(till 3rd semester) – 3.70(B-Grade) 2006 – 2009 B.Sc (Electronic Science) – Pune University - Subsidiary subject- Mathematics, Physics, Chemistry - Final Percentage – 76% [b]2005 Higher Secondary [/b]:Sangamner College, Sangamner. [b]- Subjects [/b]: Physics, Chemistry, Mathematics and Sanskrit - 49%,Maharashtra Board. [b]COMPUTER PROFICIENCY [/b]: [b]- Cadence 5.1.41(180/90nm) [/b]: Virtuoso schematic composer, Spectre circuit, simulator,Virtuoso layout editor,Virtuoso XL, Assura. [b]- Mentor Graphics [/b]: Modelsim for VHDL, Verilog. - Simulating skills in different tools like XILINX,LTSPICE,MATLAB,Keil,virtual instrumentation LABVIEW. - PCB designing experience for semester projects in M.Sc using the ORCAD tool. [b]PROJECT EXPERIENCE [/b]: [b]B.Sc Project [/b]: Microcontroller(89s52)based Automatic Car Parking The entire System is on the single PCB consisting of pair of optocoupler,display,powersupply. This system is designed to control the parking of 99 cars.It can be change as per requirement. [b]M.Sc (Project like Experiment) [/b]: 1. Design and analysis of the CMOS Inverter. 2. Layout design of all the logic gates and Flip Flop. 3. Design and Analysis of the Current Mirror and Making the Layout using Interdigitised and common centroid method. 4. Layout Design of Half Adder and Full Adder. 5. FPGA implementation using sparten-3 Kit Hands-on experience under 1 month training program during summer 2010 - Thin film deposition by CVD, Photolithography, Photo-resist coating. - Thickness measurement of Thin films using Four Probe method and Diffraction of Fringes, - Oxidation on Silicon Wafer, Plasma Ashing. INTERSHIP At C-MET (Center for Materials for Electronics Technology), Pune. [b]Project Title [/b]: “Development Of Lead Free Solder Bumping by Electroplating Method”. - Electroplating method is selected to increase the number of I/O’s it help to reduced the bump pitch. [b]- The targeted bump size was 25µm place at 75µm pitch. The work element mainly involve [/b]: 1. Setting up of Photolithography process. 2. Deposition of Solder Film And it’s Optimization. - The Use of the solder Bump is in BGA, Flip Chip Technology OTHER SKILLS AND ACHIVEMENTS Participated in “ELECTRA”. Participated in intercollegiate Science Festival , Secured prize in dance competition. [b]Conference and Workshop Attended [/b]: Attended national conference on renewable energy sources NSPTS (National Seminar on Physics and Technology of Sensors) conference at pune. Three days technical workshop on ASIC design at MIT, Pune [b]LINGUAL SKILL [/b]: English, Hindi, Marathi [b]INTREST [/b]: Singing, Dancing. I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility of the above mentioned particulars. [b]Date [/b]: (Mohini Vilasrao Somvanshi) ------------------------------------------------------- [b]More Information about this submission and submitter [/b]:- ___________________________________________________ [b]Submission ID [/b]: 4327275 [b]Date & Time [/b]: 4th Jul 2011 6:58 AM (UTC) [b]IP Address [/b]: 115.242.25.240 Browser Info : Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; AskTbBGM/5.11.3.15590) Predicted Country : India[/QUOTE]
