www.qualispace.com Pvt Ltd Thane : Graphic Designer
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  1. October 4th, 2010, 11:14 AM Post Count Number #1
    muthukalee
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    www.qualispace.com Pvt Ltd Thane : Graphic Designer

    Graphic Designer

    Candidate profile

    Creative Designer Well versed with the following
    * HTML
    * 2D design packages by Adobe, Macromedia Dreamweaver MX, etc
    * Well versed with Flash MX
    * Well versed with web design concepts
    * 2+ years experience in designing websites / logos / banners / brochures is required.

    Job Description
    QualiSpace is developing path-breaking software in the Internet Provisioning and management industry.

    Some of the types Projects you would be working on -
    Linux Hosting Control Panel
    Windows Hosting Control Panel
    Mail Hosting Control Panel
    Database Hosting Control Panel
    Payment Gateway Services
    Business Process Automation Software

    Location : Thane - Mumbai - India

    Salary : Industry Standard

    Please post us your resume at : Jobs@QualiSpace.com

    About us :
    QualiSpace - a unit of QuantumPages Technologies Pvt. Ltd, a leading company with service provisioning ability on a multitude benchmark of Internet based services such as Dedicated Servers, Managed Services, Domain Registration, Web Hosting, E-mail solutions, Anti-Virus Email Solution, Anti-Spam Email Solution, Digital Brand Management Services, SSL Certificates, and many more.

    Contact us :
    QualiSpace
    Jyoti Bldg,
    B-wing, 2nd Floor,
    Behind Paradise Tower,
    Gokhale Road, Thane(W),
    Mumbai - 400602,
    India.
    http://www.qualispace.com
    Last edited by Guest-IJT; July 28th, 2011 at 01:37 PM.
  2. July 28th, 2011, 01:38 PM Post Count Number #2
    Guest-IJT
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    Name : Mohini Vilasrao Somvanshi
    Email : mohini.somvanshi AT gmail.som
    Designation / Skillset : Cadence,VHDL,Verilog,Mentor Graphics

    Resume :

    CARRER AIM :
    Be a part of goal oriented team in an organization, where my technical background interpersonal skills can lead to both, growth of company as well as my own carrier.
    EDUCATION :
    2011(pursuing) M.Sc (Electronic Science) – University of Pune
    - Specialization in VLSI Design
    - Current GPA(till 3rd semester) – 3.70(B-Grade)
    2006 – 2009 B.Sc (Electronic Science) – Pune University
    - Subsidiary subject- Mathematics, Physics, Chemistry
    - Final Percentage – 76%
    2005 Higher Secondary :Sangamner College, Sangamner.
    - Subjects : Physics, Chemistry, Mathematics and Sanskrit
    - 49%,Maharashtra Board.
    COMPUTER PROFICIENCY :
    - Cadence 5.1.41(180/90nm) : Virtuoso schematic composer, Spectre circuit, simulator,Virtuoso layout editor,Virtuoso XL, Assura.
    - Mentor Graphics : Modelsim for VHDL, Verilog.
    - Simulating skills in different tools like XILINX,LTSPICE,MATLAB,Keil,virtual instrumentation LABVIEW.
    - PCB designing experience for semester projects in M.Sc using the ORCAD tool.
    PROJECT EXPERIENCE :
    B.Sc Project : Microcontroller(89s52)based Automatic Car Parking
    The entire System is on the single PCB consisting of pair of optocoupler,display,powersupply. This system is designed to control the parking of 99 cars.It can be change as per requirement.
    M.Sc (Project like Experiment) :
    1. Design and analysis of the CMOS Inverter.
    2. Layout design of all the logic gates and Flip Flop.
    3. Design and Analysis of the Current Mirror and Making the Layout using Interdigitised and common centroid method.
    4. Layout Design of Half Adder and Full Adder.
    5. FPGA implementation using sparten-3 Kit
    Hands-on experience under 1 month training program during summer 2010
    - Thin film deposition by CVD, Photolithography, Photo-resist coating.
    - Thickness measurement of Thin films using Four Probe method and Diffraction of Fringes,
    - Oxidation on Silicon Wafer, Plasma Ashing.
    INTERSHIP
    At C-MET (Center for Materials for Electronics Technology), Pune.
    Project Title : “Development Of Lead Free Solder Bumping by Electroplating Method”.
    - Electroplating method is selected to increase the number of I/O’s it help to reduced the bump pitch.
    - The targeted bump size was 25µm place at 75µm pitch. The work element mainly involve :
    1. Setting up of Photolithography process.
    2. Deposition of Solder Film And it’s Optimization.
    - The Use of the solder Bump is in BGA, Flip Chip Technology
    OTHER SKILLS AND ACHIVEMENTS
    Participated in “ELECTRA”.
    Participated in intercollegiate Science Festival , Secured prize in dance competition.
    Conference and Workshop Attended :
    Attended national conference on renewable energy sources
    NSPTS (National Seminar on Physics and Technology of Sensors) conference at pune.
    Three days technical workshop on ASIC design at MIT, Pune
    LINGUAL SKILL : English, Hindi, Marathi
    INTREST : Singing, Dancing.

    I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility of the above mentioned particulars.
    Date :
    (Mohini Vilasrao Somvanshi)
    -------------------------------------------------------
    More Information about this submission and submitter :-
    ___________________________________________________
    Submission ID : 4327275
    Date & Time : 4th Jul 2011 6:58 AM (UTC)
    IP Address : 115.242.25.240
    Browser Info : Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; AskTbBGM/5.11.3.15590)
    Predicted Country : India