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[QUOTE=Guest-IJT;140455][b]Name [/b]: Pobbireddy Sameera
[b]Email [/b]: dheerasameera AT gmail.com
[b]Designation / Skillset[/b] : vlsi design engineer/skill set- C, Verilog HDL and Basics of TCL & PERL.

[u][b]Resume[/b][/u] :
 
[b]PROFESSIONAL OBJECTIVE [/b]:
To pursue the Technology oriented career that will give me an opportunity to learn and contribute my skills in achieving the goal of organization. 
[b]ACADEMIC RECORD [/b]:
Course Institution Board/
University Year of
Completion % of Marks
/ CGPA
M.Tech(VLSI)
Vellore Institute of Technology, Vellore
 VIT
 2011
 7/10
B.Tech(ECE)
Malineni Lakshmaiah
Engineering college,
Singarayakonda
 JNTU
 2008
 69.81
XII
Pardha Junior College, Nellore Board Of Intermediate Education
 2004
 78
 X
 Sanghamitra Vidyalayam, Nellore Board Of Secondary Education
 2002
 82
[b]EDA TOOLS KNOWLEDGE [/b]:
[b]- Tanner Tools [/b]: T-Spice, S-Edit, L-Edit.
- Xilinx ISE suite.
- Front end -- HDL designer (Modelsim, Leonardo spectrum)
- Backend – Mentor graphics (IC station and caliber)
[b]PROGRAMMING SKILLS [/b]:
- C, Verilog HDL and Basics of TCL & PERL.
[b]AREA OF INTEREST [/b]:
- Digital IC Design
- Low power IC Design
- ASIC Design
- RF IC Design
[b]PROJECT PROFILE [/b]:
[b]U.G PROJECT [/b]:
[b]TITLE [/b]: INDUSTRIAL PROTECTION SYSYTEM USING GSM.
[b]DESCRIPTION [/b]: This project develops a system, which uses mobile technology that keeps control of the various units of automobiles, which executes with respect to the signal sent by the mobile.
[b]P.G MINI PROJECTS [/b]: 
- Standard cell design of OA31.
[b]- Design of one’s counter using Verilog HDL [/b]: front end and back end design.
- Design of Booth Multiplier using Verilog HDL.
- Automatic switching on and off the lights in the corridor
[b]- Worked on IEEE paper [/b]: A Low-Power High-Speed Hybrid CMOS for Full Adder for Embedded System.
[b]P.G MAIN PROJECT [/b]: 
[b]TITLE [/b]: LOW-POWER CLOCKED-PSUEDO-NMOS FLIP-FLOP FOR LEVEL CONVERSION IN DUAL SUPPLY SYSTEMS.
[b]TOOL [/b]: Mentor Graphics (Design Architect IC)
[b]DESCRIPTION [/b]: The main objective of this project is to get reduced power supply by designing various level converting flip-flops using dual power supply. By comparing and analyzing these level converting flip-flops we design a low power clocked-pseudo-NMOS flip-flop which has better area and PDP compared to all other designs.
[b]SOFT SKILLS [/b]:
- Positive Attitude
- Capable to work in a team
- Sincere and smart worker.
[b]TECHNICAL ACTIVITIES [/b]: 
- Published a review paper on “Performance Analysis of D Flip-Flop Implemented in GDI and ACPL Low power Design Techniques” in IJAEST Vol No 5.
- Participated in the workshop on “SOC and its Signal Integrity Issues”.
- Participated in the pre-conference tutorials of the “Silver jubilee conference on communication technologies and VLSI design” held at VIT university.
 
[b]DECLARATION [/b]: 
 I honestly declare that the information furnished above is true to the best of my knowledge.
 
[b]Place  [/b]: Bangalore
Date : 15.07.11
 (P. Sameera) 
  
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More Information about this submission and submitter:-
___________________________________________________
Submission ID : 4373337
Date & Time : 15th Jul 2011 5:53 AM (UTC)
IP Address : 117.200.13.60
Browser Info : Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18
Predicted Country : India[/QUOTE]

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