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    www.acmehousing.com Acme Housing India Pvt Ltd Mumbai : Architect

    Acme Housing India Pvt Ltd
    http://www.acmehousing.com

    Keywords: Arch

    Designation: Se Architect/GM - Arch
    Experience: 10 - 20 Years
    Location: Mumbai
    Education: UG - B.Arch - Architecture
    PG - Post Graduation Not Required
    Industry Type: Real Estate/Property
    Functional Area: Architecture, Interior Design
    Posted Date: 18 Nov 2008

    Job Description
    B Arch with min 10 years experience post qualification with developers/arch firm. Should have handled planning for commercial & residential complexes. Will be required to lead a team of arch and ensure timely follow-up to get outsourced jobs complete

    Desired Candidate Profile
    Sketching, planning using Auto Cad, decision making to finalise drawings.

    Company Profile
    Since 1976, ACME Group has been studding Mumbai with landmarks in over fifty-eight projects, all colorful, sturdy, high-rise projects. Yet to add to Mumbai's grandeur are Acme's ongoing projects

    Executive Name: Vency Fernandes

    Address:
    Not Mentioned

    Email Address: jobs@acmehousing.com

    Telephone: Not Mentioned
    Last edited by Guest-IJT; July 26th, 2011 at 03:17 PM.

  2. Post Count Number #2
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    Name : Pobbireddy Sameera
    Email : dheerasameera AT gmail.com
    Designation / Skillset : vlsi design engineer/skill set- C, Verilog HDL and Basics of TCL & PERL.

    Resume :

    PROFESSIONAL OBJECTIVE :
    To pursue the Technology oriented career that will give me an opportunity to learn and contribute my skills in achieving the goal of organization.
    ACADEMIC RECORD :
    Course Institution Board/
    University Year of
    Completion % of Marks
    / CGPA
    M.Tech(VLSI)
    Vellore Institute of Technology, Vellore
    VIT
    2011
    7/10
    B.Tech(ECE)
    Malineni Lakshmaiah
    Engineering college,
    Singarayakonda
    JNTU
    2008
    69.81
    XII
    Pardha Junior College, Nellore Board Of Intermediate Education
    2004
    78
    X
    Sanghamitra Vidyalayam, Nellore Board Of Secondary Education
    2002
    82
    EDA TOOLS KNOWLEDGE :
    - Tanner Tools : T-Spice, S-Edit, L-Edit.
    - Xilinx ISE suite.
    - Front end -- HDL designer (Modelsim, Leonardo spectrum)
    - Backend – Mentor graphics (IC station and caliber)
    PROGRAMMING SKILLS :
    - C, Verilog HDL and Basics of TCL & PERL.
    AREA OF INTEREST :
    - Digital IC Design
    - Low power IC Design
    - ASIC Design
    - RF IC Design
    PROJECT PROFILE :
    U.G PROJECT :
    TITLE : INDUSTRIAL PROTECTION SYSYTEM USING GSM.
    DESCRIPTION : This project develops a system, which uses mobile technology that keeps control of the various units of automobiles, which executes with respect to the signal sent by the mobile.
    P.G MINI PROJECTS :
    - Standard cell design of OA31.
    - Design of one’s counter using Verilog HDL : front end and back end design.
    - Design of Booth Multiplier using Verilog HDL.
    - Automatic switching on and off the lights in the corridor
    - Worked on IEEE paper : A Low-Power High-Speed Hybrid CMOS for Full Adder for Embedded System.
    P.G MAIN PROJECT :
    TITLE : LOW-POWER CLOCKED-PSUEDO-NMOS FLIP-FLOP FOR LEVEL CONVERSION IN DUAL SUPPLY SYSTEMS.
    TOOL : Mentor Graphics (Design Architect IC)
    DESCRIPTION : The main objective of this project is to get reduced power supply by designing various level converting flip-flops using dual power supply. By comparing and analyzing these level converting flip-flops we design a low power clocked-pseudo-NMOS flip-flop which has better area and PDP compared to all other designs.
    SOFT SKILLS :
    - Positive Attitude
    - Capable to work in a team
    - Sincere and smart worker.
    TECHNICAL ACTIVITIES :
    - Published a review paper on “Performance Analysis of D Flip-Flop Implemented in GDI and ACPL Low power Design Techniques” in IJAEST Vol No 5.
    - Participated in the workshop on “SOC and its Signal Integrity Issues”.
    - Participated in the pre-conference tutorials of the “Silver jubilee conference on communication technologies and VLSI design” held at VIT university.

    DECLARATION :
    I honestly declare that the information furnished above is true to the best of my knowledge.

    Place : Bangalore
    Date : 15.07.11
    (P. Sameera)

    -------------------------------------------------------
    More Information about this submission and submitter:-
    ___________________________________________________
    Submission ID : 4373337
    Date & Time : 15th Jul 2011 5:53 AM (UTC)
    IP Address : 117.200.13.60
    Browser Info : Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18
    Predicted Country : India