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[QUOTE=Guest;137315][B]RESUME :[/B] M SHYAMU [B]E-mail [/B]: balashyamu AT gmail.com [B] Career Objective [/B]: Pursue a high caliber career for a mutually beneficial and continuing relationship with the organization where the job responsibilities lead to an intellectually simulating career path. [B] Education [/B]: - Pursued PG-Diploma in DVLSI from C-DAC (Center For Development Of Advanced Computing). - Pursued B.Tech (ECE) from TKR College of Engineering and Technology (JNT University) with an Aggregate of 67.73% and year of passing is June, 2010. - Pursued Intermediate Education from ANDHRA PRADESH RESIDENTIAL Junior College (Board of Intermediate Education) with an Aggregate of 87.3% and year of passing is Mar, 2006. - Completed Schooling from ANDHRA PRADESH RESIDENTIAL SCHOOL (Board of Secondary Education) with an Aggregate of 85.83% in SSC and Year of Passing is Mar, 2004. [B] Technical Skills [/B]: [B]Languages Known [/B]: vhdl, verilog, systemverilog, c [B]Operating Systems [/B]: Win 9x/2000/XP, vista [B]Projects Undertaken [/B]: [B]Mini Project :[/B] [B]Title [/B]: DATA ACQUSITION SYSTEM [B]Description [/B]: This project deals with the temperature measurement of a motor and weather monitoring. [B]Main project :[/B] [B]Title [/B]: Implementation of RC6 Cryptographic Algorithm [B]Company [/B]: PAN TECH SOLUTIONS (HIMAYATH NAGAR) [B]Description [/B]: RC6 algorithm is used for encryption of data in this project, which is designed to meet the requirements of advanced encryption Standard (AES). This project aims at the implementation of the RC6 block cipher using the VHDL and to have a fast encryption decryption engine. Encryption /decryption of the data are varied by VHDL simulator. A data which is in binary form has been demonstrated for encryption and decryption. [B] Cdac project:[/B] [B]Title [/B]: Field Programmable Gate Array Implementation of Reed- Solomon Code, RS (255,239) [B]Company [/B]: C-DAC (Center for Development of Advanced Computing) [B]Description [/B]: This paper demonstrates an FPGA implementation of the Reed- Solomon, RS (255,239), and codec architecture for the OTN G.709. The RS codec is designed to occupy the least amount of logic blocks, be fast and parameterizable. I am presenting an efficient implementation of the encoder algorithm on reconfigurable devices in addition to a non-finalized version of the decoder. Both encoder and decoder are synthesized to Fpga’s Spartan-3e. [B] Achievements [/B]: - Won FIRST PRIZE in chess at B.tech level. - Achieved MERIT STUDENT OF THE YEAR award two times in high school. - Participated in college level paper presentation on the paper ARTIFICIAL NEURAL NETWORKS AND BARCODING TECHNOLOGY. [B] Extra Curricular Activities [/B]: - Organized various Technical events at college level ( Prathibha, ECTA) - Active participation in various cultural events held at college and school level.[/QUOTE]
