Resume CV : VLSI, Virtual Instrumentation

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  1. Post Count Number #1
    On probation
    Join Date
    September 25th, 2010
    Location
    Sabitha Mohandas, Thannikuzhiyil House, Vannappuram P.O, Thodupuzha , Idukki-685607
    Posts
    1

    Resume CV : VLSI, Virtual Instrumentation

    SABITHA MOHANDAS (B.E EIE)
    E-mail : sabitha.mohandas09 AT gmail.com

    Objective :
    To work in the most challenging position with an organization that provides ample opportunities to learn and to contribute.

    Software Skills :
    Languages : C, C++
    Packages : MS Office2003, MS Office2007, Windows Movie Maker
    Windows : 98,2000, XP, XP2,VISTA,Windows7

    Domain/ Technical Knowledge :
    Control System
    VLSI
    Electronic Instrumentation
    Virtual Instrumentation

    Curriculum Project :
    Prevention of Yarn Breakage Using Embedded System :
    Description : This project is developed for Textile industry to prevent the yarn breakage. This project is done using Embedded system. And controlling the humidity, temperature, motor speed and also if any chance yarn broke means it will detect the detector.

    Curriculum Details :
    B.E in Electronic And Instrumentation Engineering with 74% from Maharaja Engineering College under Anna University of Chennai , Tamilnadu in 2010.
    Higher Secondary Education with 72% from St. Mary’s Higher Secondary School, Kaliyar under Kerala State Board in 2006.
    THSLC with 75% from Govt. Technical High School under Kerala State Board in 2004.

    Personal Details :
    Date of Birth : 10th April 1989
    Sex :
    Marital Status : Single
    Nationality : Indian
    Languages known : English, Hindi,Tamil and Malayalam
    Hobbies : Music,Cooking, Travelling.

    About Me :
    Hardworking and completely dedicated to the assignments, that is given. Can mingle with any groups and make effective contributions. Highly self confident with good communication skills.

    Declaration :
    I hereby declare that all statements made in this application are true, complete and correct to my knowledge and belief.

    Place : Thodupuzha
    (SABITHA MOHANDAS)

  2. Post Count Number #2
    Guest Poster
    Join Date
    August 14th, 2008
    Location
    Your Heart, Delhi
    Posts
    76,213

    vlsi designer

    RESUME :
    M SHYAMU
    E-mail : balashyamu AT gmail.com

    Career Objective
    :
    Pursue a high caliber career for a mutually beneficial and continuing relationship with the organization where the job responsibilities lead to an intellectually simulating career path.

    Education
    :
    - Pursued PG-Diploma in DVLSI from C-DAC (Center For Development Of Advanced Computing).
    - Pursued B.Tech (ECE) from TKR College of Engineering and Technology (JNT University) with an Aggregate of 67.73% and year of passing is June, 2010.
    - Pursued Intermediate Education from ANDHRA PRADESH RESIDENTIAL Junior College (Board of Intermediate Education) with an Aggregate of 87.3% and year of passing is Mar, 2006.
    - Completed Schooling from ANDHRA PRADESH RESIDENTIAL SCHOOL (Board of Secondary Education) with an Aggregate of 85.83% in SSC and Year of Passing is Mar, 2004.

    Technical Skills
    :
    Languages Known : vhdl, verilog, systemverilog, c
    Operating Systems : Win 9x/2000/XP, vista
    Projects Undertaken :

    Mini Project :
    Title : DATA ACQUSITION SYSTEM
    Description : This project deals with the temperature measurement of a motor and weather monitoring.

    Main project :
    Title : Implementation of RC6 Cryptographic Algorithm
    Company : PAN TECH SOLUTIONS (HIMAYATH NAGAR)
    Description : RC6 algorithm is used for encryption of data in this project, which is designed to meet the requirements of advanced encryption Standard (AES). This project aims at the implementation of the RC6 block cipher using the VHDL and to have a fast encryption decryption engine. Encryption /decryption of the data are varied by VHDL simulator. A data which is in binary form has been demonstrated for encryption and decryption.

    Cdac project:

    Title : Field Programmable Gate Array Implementation of Reed-
    Solomon Code, RS (255,239)
    Company : C-DAC (Center for Development of Advanced Computing)
    Description : This paper demonstrates an FPGA implementation of the Reed- Solomon, RS (255,239), and codec architecture for the OTN G.709. The RS codec is designed to occupy the least amount of logic blocks, be fast and parameterizable. I am presenting an efficient implementation of the encoder algorithm on reconfigurable devices in addition to a non-finalized version of the decoder. Both encoder and decoder are synthesized to Fpga’s Spartan-3e.

    Achievements
    :
    - Won FIRST PRIZE in chess at B.tech level.
    - Achieved MERIT STUDENT OF THE YEAR award two times in high school.
    - Participated in college level paper presentation on the paper ARTIFICIAL NEURAL NETWORKS AND BARCODING TECHNOLOGY.

    Extra Curricular Activities
    :
    - Organized various Technical events at college level ( Prathibha, ECTA)
    - Active participation in various cultural events held at college and school level.