System-Verilog design Verification training Bangalore : www.noveldv.com CVC

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Fast-Track course on Verification Using SystemVerilog - Bangalore
http://www.noveldv.com/

System-Verilog design Verification training : CVC : Bangalore

Company profile:
CVC is a Design Verification (DV) startup firm addressing
various aspects of DV process including (but not limited to):
Verification Methodologies
Languages for ASIC/FPGA designs
VIP (Verification Intellectual Property) development
PIP (Protocol Intellectual Property) development
Verification auditing
Resource Augmentation
Corporate and individual trainings on various Verification
techniques

Based in Bangalore, the IT capital of India, our experts serve
the Indian market as well as markets abroad (such as AsiaPac,
Eurpoe. Middle-east, Israel).


Quick facts
When: 6th or 7th June (Fri/Sat)
Where: Bangalore, CVC Office (Ground Floor)
Cost: Rs. 2500 /- onwards (See below for details)
Contact: cvc.training@gmail.com , training@noveldv.com
+91-9916176014,
+91-80-41495572


What's SystemVerilog?

IEEE 1800, SystemVerilog is the de-facto language for Digital system
Verification (and Design).
Almost every ASIC team is either using it or plan on using it in the
next project!

It is a major extension to Verilog-2001, adding significant new
features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.


What's a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations
aimed at getting to the core of the subject ASAP. CVC's Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?
Practicing Design and Verification engineers with tight project
schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.


What's the cost?
That is a no-brainer question, isn't it? We understand and appreciate
the cost conscious landscape of our region. That's why we have innovative cost structure as shown below.


The basic cost of this course is Rs. 4,000 /- per attendee. As a
limited period offer, we are glad to announce "The more-the-merrier" scheme. If you pool in more folks you get more discounts. For every other attendee that you bring along, you get Rs. 500 /- discount - for BOTH the attendees (subjected to a minimum of Rs. 2500 /-), can it get better than this ?


Here is a simple table showing the offer in numeric:

No. of attendees | Cost per attendee | Your savings (total)
2 3500 1000
3 3000 3000
4 (and above) 2500 6000+

Venue details
CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:
Friday 6th June at 8.30 AM
Saturday 7th June at 8.30 AM


How do I register for a class?
To attend this class, confirm your registration by sending an email
to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:


Name:
Company Name:
Official Email ID:
Contact Number:
Preferred Date: 6th or 7th June (Friday or Saturday)

Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using
SystemVerilog are originally
designed for 3 variants:
* A 10-day class with extensive labs and a complete project (suitable
for students, jobseekers)
* A 3-day class and
* A 2-day class
So, depending on how much time you can invest, you pick the one
appropriate to you.
Needless to say - the more time you invest, the better you master this
amazingly powerful language.


Trainer Profile
Ajeetha Kumari, Design Verification Consultant
* Has 8+ years of experience in Verification
* Co-authored leading books in the Verification domain.
* Presented papers, tutorials in various conferences, publications and
avenues.
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV
and OOP for Verification
* Holds M.S.E.E. from prestigious IIT, Madras.

[Guest]

CURRICULUMVITAE
Email id : yogananda408 AT gmail.com
YOGANANDA REDDY YERRI
Objective

I am looking for a long term career path with challenging assignments that will
strengthen my knowledge and for an environment that gives freedom to implement my own
ideas and gives excellent career growth.
Academic Credentials
- B.Tech Graduation completed with 64.0% E.C.E specialization from M.R.R Institute of Technology and Science, Udayagiri, Nellore in 2010.
- Diploma completed with 67.0% E.C.E specialization from Govt Polytechnic. College, Proddatur, Kadapa in 2007.
- S.S.C completed with 70.0% from Gnanodaya High School, Madanapalli, Chittoor in 2004.
Technical Skills
Operating Systems : Windows
Languages : C , VerilogHDL
Electronic Design Package : Xilinx ISE, Model SIM.
Microcontrollers/CPLD/FPGA : XilinxFPGA(Spartan3,Spartan3E,Spartan6)
PROJECTS SUMMARY :
Academic Project
Title of the Project : Voice Controlled Wheel Chair Robot
Description :
A robot is a reprogrammable multifunctional manipulatordesigned to move material,parts,tools through variable programmed motions.The proposed project enables physically challenged persons.They can move in there own directions,without any third party’s help.It additional feature voice enabled.It will contain an inbuilt mic and recognition system,which will do the fuctions like left,right,forward & reverse operations.It also contains a themistor which will moniter and record the temperature in the LCD panel.It has most advanced feature of the poject,data is received by RF receiver comdined with a microcontroller and an LCD panel also.
Professional Course
I have completed Development program on VLSI Design from Sandeepani School of VLSI Design, Bangalore.
Projects During Course :
VGA Controller using FPGA
4-bit processor using VERILOG
Strengths
- Ability to think Logically.
- Highly dedicated and self-motivated
- Ability to Mingle with people in friendly attitude
- Positive Thinking, Pre-Planning, Committed & willing to take up challenges.