Han Digital Solution Pvt.Ltd, Bangalore

Name of the Designation: Parasitic Extraction (PEX) Professionals
Location: Bangalore
Education: BE/ BTECH / ME / MS / MTECH
Business Group: Research Team
Industry: Semiconductor Jobs
Approx Hiring time in weeks: 30

Company Profile :
The BU for which this position is looked up for is responsible for the definition and development of industry leading technologies such as Copper Interconnect, Silicon on Insulator (SOI), High-Performance Logic-Based Embedded DRAM technologies, and SiGe for RF and analog applications, and high-k material technologies. This is also the leading organization in defining the most advanced technologies for the 45 nm and 22 nm nodes, including research in various aspects of Lithography, strained silicon, and Magnetic RAM (MRAM). This particular BU of our client develops all of our client’s semiconductor technologies including SOI, Bulk CMOS, RFCMOS, HVCMOS, SiGe HBT BiCMOS, and nanodevice technologies

Skills:
Key Skills:PEX, StarRCXT, QRC, "Mentor xRC", Claibre, assura, PVS
Must have Skills:PEX, StarRCXT, QRC
Good to have Skills:perl, tcl, python, raphael, FastHenry, QuickCap
Roles and Responsibilities :
** M. Tech. / MS in Electrical Engineering, Physics, or Computer Engineering
** Experience in electro-magnetics, parasitic extraction, or device physics
** 2+ years of development experience in parasitic extraction decks (Synopsys StarRCXT, Cadence QRC, Mentor xRC) and LVS (Hercules/ICV, Cadence Assura/PVS, Mentor Calibre)
** 2+ years of experience with field solvers (e.g. Raphael, FastHenry, QuickCap, or similar tool)
** 2+ years of experience with scripting languages (e.g. Perl, TCL, Python)

Name of the Designation : Sr.Technologist
Location: Bangalore
Education: PhD / MS
Industry: Semiconductor Jobs
Approx Hiring time in weeks: 30
Skills :
Key Skills:Computational lithography, Device Physics, Process characterization
Must have Skills:Computational lithography, Device Physics, Process characterization
Good to have Skills:Process Integration
Roles and Responsibilities :
** Our client’s research team has multiple mission critical responsibilities in the area of Device & process Characterization, Computational Lithography, eDRAM design at each of the bleeding edge technology nodes.
** Team works very closely with Fab and Global development engineers.
** However, there's a need to integrate various efforts in each technology node within India research team.
** We're looking for an experienced technical lead who has proven industry track record of process integration / technology development / technology transfer working for multinational semiconductor manufacturing company.
** The candidate should have experience of leading a team of engineers, has in-depth knowledge of bleeding edge (45nm and beyond) semiconductor process details, lithography, device engineering, characterization.
** A doctoral degree in EE preferred, The experience level should 7-8+ years in industry post PhD, MS candidates are ok if backed up with research credentials in addition to industry experience.

Name of the Designation: OPC Professionals
Location: Bangalore
Education: BE / BTECH / BS / ME / MS / MTECH / Ph.D
Business Group: R&D
Industry: Semiconductor Jobs
Approx Hiring time in weeks: 30
Skills :
Key Skills:OPC, Litho, computational lithography, calibre, DRC, LVS
Must have Skills:calibre, DRC, LVS, "physical verification", OPC, lithography, scripting
Good to have Skills:calibre, DRC, LVS
Roles and Responsibilities :
JD for 2 to 5 Years :
** Good experience in Physical verification methods DRC / LVS
** Extensive Hands on experience in caliber tool
** Should be having good knowledge in scripting TCL, Perl or shell
** Having exposure in Litho or Fabrication process would be added advantage

For Exp > 6 years:
** Interact with integration and design teams to provide optical proximity corrections on design patterns and improve manufacturability.
** Lead team to develop new techniques (including scripts and tools) to address technology issues and keyword challenges
** Candidate should have knowledge in RET, design technology co optimization with exposure to 45nm, 32nm technologies
** Ability to interface with lithography, integration and design teams
** Knowledge of physical design, layout and routing is desirable.
** Strong leadership skills with technical depth required, exp with global team is a plus
** Experience with physical verification tools such as Mentor Calibre, SVRF, Cadence Assura and / or Cadence Virtuoso, C/C++ coding and shell / TCL/ Perl Scripting and OOP is a plus

http://handigital.com/jobs

Contact Us:
Han Digital Solution Pvt Ltd,
# 4 & 5, 1st & 2nd Floor,
1st Cross, Krishna Reddy Colony,
Domlur Layout,
Bangalore - 560 071

If you meet the above criteria, please email your detailed curriculam vitae with a cover letter to : dana@handigital.com