Engineer, Memory Layout Design :
Education Requirements : Diploma in Electronics Or B.E/B.Tech/ M.E/M.Tech in Electronics Engineering

General Description :
Candidate is expected to contribute individually by working hands-on layout design of SRAM/ROM/CAM/Custom memories and physical verification of memories. He/She is expected to mentor/lead team of memory layout designer depending on requirement of project. Candidate is required to interact and work with customer projects at their work place.
Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Work Experience Requirements :
Candidate must have experience in layout design of memory leaf cells and at top level of memories
He/She should have worked on 65nm/45nm/28nm process technologies and have understanding of issues like WPE, LOD effects
He/She must have good understanding of physical verification checks - DRC, LVS, ERC and reliability checks - IR and EM
He/She must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks
He/She must have good understanding of Basics of CMOS circuits
Preferable candidate to have Skill and perl scripting experience to develop layout and schematic tiler
He/She should have minimum of 4 - 8 years of experience


Engineer, Memory Characterization :
Education Requirements : B.E/B.Tech/ M.E/M.Tech in Electronics Engineering

General Description :
Candidate is expected to work as individual contributor on characterization of memories for single port/dual port/register files/CAMs etc. Job require to develop test stimuli, spice decks, circuit simulation for timing and power, mis-match, margin simulations, bit cell analysis and debugging, and Monte Carlo simulations etc. Candidate must have good understanding in generating EDA views of memories. Candidate must have good experience in QA process for release of .libs and models.
Candidate is required to interact and work with customers on their projects either at our office or customer's work place.
Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Work Experience Requirements :
Candidate must have transistor level circuit design experience of memories
He/She should have worked on 65nm/45nm/28nm process technologies and must have understanding of design issues related to process.
He/She must have good understanding of layout design of memories
He/She must have worked on transistor level circuit simulation tools like Hspice/Hsim/Nanosim and characterization tools Altos/Magma to generate timing views and models
He/She must have good understanding of circuit design concepts for low power CMOS circuits
Preferable candidate to have understanding of front end memory models generation and validation
He/She should have minimum of 2 - 7 years of experience
Scripting experience in Perl is desirable

Engineer, Memory Circuit Design :
Education Requirements : B.E/B.Tech/ M.E/M.Tech in Electronics Engineering

General Description :
Candidate is expected to work individually or lead team of engineers on design of memories - single port/dual port/register files/CAMs etc. Job requires to do transistor level design to build low leakage and high performance memory compilers. He/She should have worked and understanding of bit cell analysis and full flow/methodology for compiler design. Candidate is expected to work with silicon validation team to debug design issues on silicon.
Candidate is required to interact and work with customers on their projects either at our office or customer's work place.
Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Work Experience Requirements :
Candidate must have transistor level circuit design experience of memories
He/She should have worked on 65nm/45nm/28nm process technologies and must have understanding of design issues related to process
He/She must have good understanding of layout design of memories, physical verification and reliability checks
He/She must have worked on cadence tools for layout design and Cadence/Mento /Synopsys tools for circuit simulation
He/She must have good understanding of circuit design concepts for low power CMOS circuits
Preferable candidate to have understanding of front end memory models generation and validation
He/She should have minimum of 2 - 7 years of experience

We are always looking for qualified people with a drive to succeed. Please send your resumes to : hr@interradesign.com.

http://www.interradesign.com/career.php

Contact Us :
Interra Systems
Kalyani Platina, No.24, Phase I, 2nd Floor,
EPIP Zone, Whitefield,
Bangalore – 560066