Synopsys
http://www.synopsys.com

Keywords: Verification, System verilog, Front end Verification

Company Profile
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in delivering semiconductor design software, intellectual property (IP), design for manufacturing (DFM) solutions and professional services that companies use to design systems-on-chips (SoCs) and electronic systems. The company?s products enable semiconductor, computer, communications, consumer electronics and other companies that develop electronic products to improve performance, increase productivity and achieve predictable success from systems to silicon.

Design Engineer (Verification, System Verilog, Front-end Verification)
Experience:
3 - 8 Years
Location:
Bengaluru/Bangalore
Education:
UG - B.Tech/B.E. - Any Specialization, Computers, Electrical, Electronics/Telecomunication

PG - M.Sc - Any Specialization, Electronics;M.Tech - Any Specialization, Computers, Electrical, Electronics/Telecomunication
Industry Type:
Semiconductors/ Electronics
Functional Area:
Embedded/EDA /VLSI/ASIC/Chip Design
Posted Date:
16 Sep


Job Description
The consultant should be an expert in using Synopsys EDA tools on a customer project in front-end, verification, design for test and SoC design. The consultant should be able to contribute to both off-site projects and provide significant expertise to customer design teams. Expert in one or able to independently deliver more than one of the service line offerings. Able to drive technical area of SPS Core Team in the development of a new offering. Fruitfully probes diverse sources for answers to technical problems. Keeps composure during crises, doesn't get frustrated and can comfortably handle risks and uncertainty. Works and sets expectations under limited direction with no instruction on routine work. Leads self or small team (less than 3) in delivery of project based on one of the Service Line Offerings. Mentors less experienced consultants. Works with CM, PM, TSM and Sales team to extend or expand Customer contract. Supports TSM in business development as required. Expected to write papers for technical conferences. The consultant should be an expert on system Verilog or Vera test bench development. He/she should have experience with constraint and random based verification methodologies.

Desired Candidate Profile
BS with 6 - 7 yrs relevant experience. MS with 5+ yrs relevant experience. Related Ph.D. with 3+ yrs. Essential that the individual demonstrates strong communication, verbal and written, and awareness of project management issues.

Executive Name:
MItty Cherian

Address:
Not Mentioned

Email Address:
mitty.cherian@synopsys.com

Telephone:
Not Mentioned