www.cadence.in Design Systems India Pvt Ltd Bangalore : Project Architect, Interior Design

[mskavi]

Cadence Design Systems India Pvt Ltd

Company Profile
A well established, young architecture and interior designing practice, doing contemporary work and recipient of awards at national level.

Project Architect
Experience: 1 - 4 Years
Location: Bengaluru/Bangalore

Job Description
Committed to designing and supervising architecture and interior projects.. Competency in understanding and implementing various detail and technical drawings. Effective communication and people management skills are essential to interact with clients and coordinate with contractors.

Desired Candidate Profile
A right blend of creative sensitivity and technical competence with strong desire to create high quality work, ability to work as team member. Basic knowledge about structure and services are essential.

Email Address: narendra@cadence.in smaran@cadence.in
http://www.cadence.in

Keywords: Project Architect, Interior Design, Architect, B Arch, M Arch

[harini]

Hi I am harini. I have 5 experience in Architecture interior and master planning, landscaping designs.
So now i m sending my resume plsea find attached.

Thanks & Regards,
Harini.v.

[Ranganathan .S]

RANGANATHAN .S
#37, 33rd Main, 5th Cross,
BTM 1st Stage,
Bangalore – 560068 Mobile : +91 – 9916737692
Karnataka, INDIA. Email : ranganathan86 AT gmail.com

Objective
To become a result oriented professional by utilizing the opportunities and make noticeable contribution in the Research - oriented fields of VLSI.
Professional Summary
- Develop Assertions using Property Specification Language (PSL) for Static and Dynamic Verification and validate them
- Identify and validate the deadcode in the RTL design
- Validate a protocol that implemented in the design using FVIP
- Good hands on RTL coding (VHDL and Verilog) and PERL scripting (File Handling, Writing and Reading the Excel, Array Variables, Handle File Systems, Formatting the output, Hashes)
- Good knowledge and experience in using ModelSim and Incisive Formal Verifier (IFV)
- Good knowledge in CMOS Backend Design (Full Custom Design)
- Worked on VLSI tools during Master degree (ModelSim, VCS, Xilinx ISE, Synopsys Design Compiler, Astro and Virtuoso Schematic and Layout Editor)
Industrial Experience
Trainee Design Engineer (Jul’08 - July’09) – NOKIA India Pvt. Ltd. (ASIC Team), Bangalore
Project Title : Design & Verification of Bus Bridge between OCP and AHB
Team Size : 1 Duration : 6 Months
Tools : ModelSim and Incisive Formal Verifier (IFV)
Description : OCP and AHB protocols are modeled using VHDL and their functionality is verified with simulations. To interface these modeled protocols, a Bus Bridge is designed and simulated for desired functionality. To verify the design, both static and dynamic PSL assertions were developed for OCP, AHB and Bus Bridge and are proved using the IFV and ModelSim tool respectively.
Project Title : Design of OCP Arbiter and Clock Bridge
Team Size : 2 Duration : 2 Months
Tools : ModelSim
Description : OCP Arbiter design coded in VHDL acts as an interface between two masters and one slave, working at two different clocks. To accomplish the need of synchronization of OCP signals between the master and slave, the Clock Bridge was designed.
Educational Profile
- Master of Science [Engineering] in VLSI System Design in 2009 from Coventry University, UK with Merit
- B.E in Electrical and Electronics Engineering in 2007 from ANNA University, Tamil Nadu with Distinction
- Higher Secondary [2003] in Computer Science group from Bharathi Vidhyalaya Higher Secondary School, Salem, Tamil Nadu with an aggregate of 82.64% (first class)
Academic Projects
Project Title : Design of Dual Elevator Controller
Team Size : 2 Duration : 1 Months
Tools used : Modelsim and Xilinx ISE
Description : The FSM for the dual elevator is constructed and used to develop the Verilog code using Moore machine technique. The design was validated for various cases using suitable test vectors. The design was implemented at SPARTAN III FPGA board and was tested with the same test vectors for same functionality.
Project Title : Design and Validation of ATM Controller
Team Size : 2 Duration : 2 Months
Tools used : Modelsim
Description : The block diagram of the ATM controller was designed and the FSM for the same was build. SystemVerilog code for the built FSM was developed using enumerated data type. The design was simulated using suitable test bench, developed to validate the various modes of operation of the ATM controller.
Project Title : Synthesis & Implementation of 16-Point Radix-4 FFT Algorithm
Team Size : 2 Duration : 2 Months
Tools used : Design Compiler, DFT Compiler, PrimeTime, Formality & Astro
Description : Verilog code for 16-point radix-4 FFT Algorithm is synthesized using TSMC 0.18µm technology with optimal constraints using Design Compiler (DC). Scan-chain insertion and STA were carried out after which Area and Power was compared. The design is formally verified after synthesis for its functionality using Formality tool. The P&R for design is carried out and Power Analysis was performed using Astro tool.
Project Title : RTL Design of 8Kb (1K-byte) Dual Port SRAM
Team Size : 2 Duration : 1 Months
Tools : Modelsim
Description : The Verilog HDL was developed for a dual port 1K memory location, each storing a byte of data. Test bench was developed to validate the design for the different operating modes of the dual port SRAM.
Project Title : Schematic Design and Layout Implementation of 4x4 6T SRAM
Team Size : 2 Duration : 2 Months
Tools : Virtuoso SE, Spectra, Virtuoso LE, VXL and Assura
Description : The 6T SRAM cell was designed and simulated. The various periphery blocks were identified, designed and simulated for the desired functionality. The layout for the designed logic was done in priority of area, power and speed. The DRC & LVS was completed and post-layout simulation was carried out.
Project Title : Design of 5-bit ADC-DAC System
Team Size : 2 Duration : 2 Months
Tools : Virtuoso SE, Spectra, Virtuoso LE, VXL and Assura
Description : A 5-bit Dual-slope Integrating ADC and Thermometric DAC were designed and simulated for the desired functionality. The layout for the various blocks were developed and verified for DRC and LVS. The blocks were integrated to build the top-level ADC and DAC blocks. The DRC & LVS was completed for integrated ADC & DAC blocks and the post-layout simulations were carried out. The INL and DNL are measured as performance figure of the design.
Strengths
- Team player
- Target and achievement oriented with an ability to take up challenges and perform in challenging work environments
- Unique blend of technical and interpersonal skills combined with proficiency in MsOffice Suite
- Quick Learner
Personal Details
Languages Known : English, Tamil
Date of Birth : 21st May 1986
Marital Status : Unmarried
Passport Number : G0836609
Nationality : Indian
Permanent Address : S/o R. Sundaram, 62/50, 2nd Market Street
Ammapet, Salem – 636003, Tamil Nadu, India

I hereby declare that the above-furnished information is true and genuine to the best of my knowledge.

Place: Bangalore Ranganathan .S

[Guest]

hello guys,
i´ve a question, what is bengalore? im listening to much people talking about it. could you explain me?