www.smart-dv.com SmartDV Technologies India Pvt Ltd Bangalore : Verification Engineer

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    www.smart-dv.com SmartDV Technologies India Pvt Ltd Bangalore : Verification Engineer

    Name of the Company : SmartDV Technologies India Pvt Ltd (smart-dv.com)
    Job Title : Verification Engineer
    Job Location : Bangalore
    http://www.smart-dv.com/careers.html

    Career
    At Mogae, we offer an environment where a person not only has the opportunity to interact and learn from seniors in his/her chosen field, but also an atmosphere where new ideas are encouraged and when proven business worthy are seen through to their implementation.
    SmartDV offers a unique opportunity for ambitious ASIC engineers.

    Verification Engineer :
    ** 2-7+ Years of experience in ASIC verification
    ** Should have tapped out atleast 1 chips from specs to post silicon debug
    ** Should have experience in creating testbenches from scratch
    ** Should have very good understanding of coverage driven verification closure
    ** Strong knowledge of Verilog, HVL (VERA or SystemVerilog or e (Specman))
    ** Very good experience in writing scripts in Perl or Python or TCL
    ** Independent team player with excellent communication skills
    ** Knowledge of C++

    Design Engineer :
    ** 2 to 7+ Years of experience in ASIC design
    ** Expertise in micro-architecture, design of design blocks (IP) to system-on-chip (SoC) components
    ** Experience in one/more of the following system bus interfaces like PCI Express, USB, SATA, SDIO, MIPI and /or AMBA.
    ** Knowledge of SVA
    ** Knowledge of memory controllers, CPU architecture is a plus
    ** Knowledge of considerations for performance, power and cost optimization is desirable
    ** Looking for highly motivated individuals and ability to deal with ambiguity
    ** Ability to work in a team environment
    ** Good debugging and problem solving skills
    ** Ability to work with external technology companies for combined development of SOCs
    ** Strong knowledge of Verilog
    ** Very good experience in writing scripts in Perl or Python or TCL
    ** Independent team player with excellent communication skills

    Engineer Trainee :
    ** B.E or MTech from reputed university with 0-2 years experience.
    ** Strong understanding of Digital design
    ** Working experience with Verilog or VHDL or SystemVerilog
    ** Experience in writing C or C++
    ** Understanding of OOPS.
    ** Knowledge of Perl or Python or TCL scripting languages
    ** Very good academic track record

    How to Apply :
    Send resumes to jobs@smart-dv.com

    Contact us :
    SmartDV Technologies India Pvt Ltd
    #14/B, 2nd Cross, SR layout,
    Murgeshpalya,
    Bangalore - 560017,
    India

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    What are the requirements that need for ece diploma students?

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    What are the jobs given to diploma holders about salary working times?