www.smartplayin.com SmartPlay Technologies Pvt Ltd Bangalore : RTL Design Engineer

[STSRekha]

SmartPlay Technologies (I) Pvt. Ltd.
smartplayin.com

RTL Design
JobCode :RTL Design
Designation :RTL Design
Location : Bangalore
Qualification : BE or ME / MTech / MS in Electronics or Electrical
Experience : 3- 8 yrs
No of Posts : 15
Description :
Experience with standard cell ASIC and / FPGA design.
Candidate should be familiar with RTL and gate level design and verification using VHDL and/or Verilog hardware description languages.
Basic understanding of CMOS ASIC fundamentals
Knowledge of all phases of ASIC design methodology
Module Level Designs - Micro Architecture, Design, Verification
SoC Integration
SDC, Timing Analysis
Verilog / VHDL
Linux/Unix environment
Team Player
Good Communication Skills
Desired Capabilities
Knowledge of Bus Protocols like AXI, AHB, SPI, USB, and Ethernet Protocol
Familiar with ARM microprocessors
Knowledge of System Verilog
FPGA based designs
Test Planning & Verification

Design Verification
JobCode : Design Verification
Designation : Design Verification
Location : Bangalore,Hyd,Noida,Malaysia and USA
Qualification : BE or ME / MTech / MS in Electronics or Electrical
Experience : 2 - 8yrs
No of Posts : 90
Description :
Proficiency in one or more HVL's a must (System Verilog, C++, Vera, e, System C, test builder).
Strong domain knowledge on one or more - PCIe, USB, Ethernet, ARM, AHB/AXI, AMBA
Should have worked on SOC verification on at least one project with constrained random methodology (eRM/VMM/OVM).
Must be expert in building a verification env with any of the above methodology, writing and debugging test cases.
Good in concepts Code coverage and functional coverage.
Expertise in Verilog and / or VHDL is desired
Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc

Physical Design
JobCode : Physical Design
Designation : Physical Design
Location : Bangalore,Hyd,Noida,Malaysia and USA
Qualification : BE / MS or ME / MTech / MS in an Electronics / Ele
Experience : 2-10yrs
No of Posts : 30
Description :
Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm & 65nm)
Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout .
Clear understanding and command over all aspects of physical design
Expertise in Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter
Skill and experience in scripting using Tcl or Perl desirable

Contact us :
SmartPlay Technologies (I) Pvt. Ltd.
Semiconductor Division
5th Floor, Golden Towers
Kodihalli, Old Airport Road
Bangalore - 560 017

Web : http://www.smartplayin.com

[Snehal.patil1986]

Dear Sir/Mam,
Please send email id so that I can attach my CV here.(EXP :3 yrs AS FPGA VLSI VHDL Engineer)
Thanks.
My id : snehal.patil1986 AT yahoo.co.in ,
1)Expected CTC : As per industry standard.
2)Notice Period : 1 day. My last job was a contract of 3 yrs. Now that contract is expired.
3)Preffered job location : anywhere in India
4)skills : FPGA,VHDL,IP,ChipScope,ModelSim,JTAG,Xilinx,SPARTAN,Xilinx ISE simulator