Vulnur Technosoft Bangalore, Hyderabad, Pune : HSPICE, Finesim, Verilog, Cadence Schematic, Layout editor, StarRC - XT Custom Design Engineer

[Admin]

Vulnur Technosoft

Company Profile
Vulnur Technosoft is the worlds largest supplier of innovative flash memory data storage products. Serving both consumers and original equipment manufacturers.



Experience:
1 - 3 Years
Location:
Bengaluru/Bangalore, Hyderabad / Secunderabad, Pune
Education:
UG - B.Sc - Electronics;B.Tech/B.E. - Any Specialization

PG - M.Sc - Computers, Electronics;M.Tech - Any Specialization
Industry Type:
IT-Software/ Software Services
Functional Area:
Embedded/EDA /VLSI/ASIC/Chip Design
Posted Date:
11 Aug


Job Description
Candidates will work with the Flash design team in Sunnyvale to architect, design and develop NAND Flash memory products utilizing state of the art non-volatile technologies. Design, simulate, and verify critical circuits like Oscillators,IO buffers.


Desired Candidate Profile
1 to 2 Years of experience in custom Digital design/ Timing Verification / Standard cell Development / Macro Cell Development /IO Design.Thorough understanding in MOS device physics and interaction between design, device, reliability and process.

Executive Name:
Reetu HR

Address:
Not Mentioned

Telephone:
Not Mentioned

Keywords: HSPICE, Finesim, Verilog, Cadence Schematic, Layout editor, StarRC - XT, Calibre xRC, Timing Verification, IO Design.

[prathyushalk]

CURRICULUM VITAE

Email-id: preeti.luck06 AT gmail.com
PRATHYUSHA L.K.

Objective:
To work in a creative and challenging team environment in industry where my formal education, technical skills will always be utilized and give me an opportunity to learn more and enhance my skills.

Academic Qualifications:
Qualification University/Board Year Percentage
BSc (Computers) Sri Venkateswara University. 2008 70%
Intermediate Board Of Intermediate Education. 2005 66%
S.S.C Board Of Secondary School Education. 2003 78%

Technical Skills:
Operating Systems : WIN XP
Languages : C, C++, JAVA
Database : DBMS, MS-ACCESS, ORACLE-9i, SQL Server
Internet Tools : HTML, Java Script.
Frame Work : .NET 3.5 (Still Persuing)
Packages : MS-Office 2003, 2007

Strengths:
- Quick Learning
- Good Presentational, Communication and Inter Personal Skills
- Have an ability to integrate into and work in teams
- Possess leadership skills

Declaration:
I here by declare that the information given above is true to the best of my knowledge and belief.


Date:
Place: Hyderabad

(L.K. PRATHYUSHA)

[Guest]

Email: kashyapjyoti AT gmail.com

Objective:

To work in a challenging environment where learning curve is higher and I can employ my skills to the best and in an effective manner.

Achievements:

Awarded “Qualstars”, Qualcomm’s internal awards for excellence in Quality of Work and meeting deadlines continuously in various projects.
Experience:

I have 2+ years of experience in architecting Standard Cell libraries and Formulating
Physical Verification Flows for the libraries at Qualcomm CDMA Technologies (QCT).
Scope of Work:

- Involved in architecting standard cell libraries which involved issues like deciding on cell height, area usage, and metals to be used and performance.
- Worked on various standard cell layouts in different foundries and technologies like
TSMC, IBM etc.
- Making pcells using both graphical method and using SKILL.
- Worked on Commercial chips as well as various Test chips.
- Worked on various kind of Database Translators(DBT).
- Experience in handling various ECOs.
- Latest interests: Adiabatic circuits.

Project Summary:
Project Names for various Standard Cell Libraries. 65nm,45nm,28nm
Standard Cell library.
Position Engineer
Description
- Layout design and physical verification checks for High Vt 28nm library cells, designed flops migrated from 45nm library.
Layout Design and physical verification checks for complex and combinational Cells in 32nm high Vt library.

Flop,latch,OAI,XOR,Full adder,etc .

- Custom block layout design for Register Array in 45nm using flop and latch based archeitecture.The different flavors designed are
8X8,16X8,4X8,2X8,16X16,8X16,4X16,2X16

- Worked on test chip for 45nmm Technology.
- Layout Design and physical verification checks for complex cells in 45 nm (Ultra High Density Lib) TSMC ,high Vt library.The cells designed are High drive strength flops, latch, Adder, MUX, Combinational cells, balanced clock,clock gating cells,ultra high speed flops,scan flops,ringoscillator,custom blocks,double height cells,etc .
- Written SKILL program for top level DRC verification for 8 track library for 45nm (Ultra High Density Lib) .
- RF library development( High Vt ,Low Vt, nominal Vt ),45nm. Project Lead for the entire library. Design layout and entire library release of 2059 cells .
- RF library development( High Vt ,Low Vt, nominal Vt ),180nm. Project Lead for the entire library release of 500 cells for TSMC and Chartered foundary.
- Layout design of global control block of SRAM for MEM chip 65nm using Pcells.
- Written SKILL program to identify the pins and draw the pins attach the text to pins and generate the abstract view ,add abstract property and generate the LEF file for 800 cells of a library from Taiwan vendor library.
- Layout Design and physical verification checks for high Vt , low Vt, nominal Vt library cells in 45nm (High Performance Lib).Layout design of High drive strength flops, latch, Adder, MUX, Combinational cells,balanced clock,clock gating cells,ultra high speed flops,scan flop ,ringoscillator,custom blocks,double height cells,etc.
- Layout Design and physical verification checks for high Vt , low Vt, nominal Vt library cells in 45nm (High density Lib).Layout design of clock gen cells, flops, latch, Adder, MUX, Combinational cells,custom blocks,triple height cells, etc .
- R & D on 9 track to 8 track conversion for 45nm tech. Had designed layout for highly used top 20 cells and redsigned the layout with 8 track architecture. The area is compact by 10-12 % and timing is slightly more than the 9 track archeitecture .Designed flops, latch, Adder, MUX, Combinational cells, etc.
- Layout Design and physical verification checks for complex and combinational
Cells in 65nm high Vt and low Vt library. Flop, latch, MUX, adder, Clock gen cells, combinational cells,etc.

Responsibility - Done physical architecture of the standard cell library like deciding on Cell Height, Metals to be used, track height and routing pitch etc.
- Done Layouts for various Logical circuits like muxes, adders, flip flops etc.
- Analysis of various effects like Electromigration , Antenna violations ,Crosstalk etc.
Technical Skills:
Operating System Windows 2003, XP, Solaris 9, Linux
Tools Cadence Tools: Virtuoso Layout Editor, Virtuoso XL ,Schematic Composer,STARCXT and other In-House tools.
Mentor Graphics Tools: Calibre for DRC,LVS,ERC,Softcheck etc.;Calibre_drv.,RVE
Languages SKILL,Perl,C
Application Outlook 2003,Eudora,Mozilla,Netscape ,Meeting Maker etc.


Soft Skills:

- Good interpersonal and communication skills.
- Team Management skills.
- Presentation skills.
- Fast learner.
- Flexibility.
- Team Spirit.
- Determination & Dedication.
- Optimistic.
- Good grasp of business processes and functionality.
- Hard worker and a good team player with excellent work ethic.
Education Details:
Post Graduation
M.Tech (VLSI Design) 2004 – 2006
C-DAC, Noida affiliated from Indraprastha University, Delhi, India
Percentage – 73.6%
Post Graduation
M.Sc.(Electronics) 2001 – 2003
Department Of Electronics Science, South Campus, Delhi, India
Percentage – 62%
Graduation
B.Sc.(Electronics) 1998 – 2001
Deen Dayal Upadhyaya College, Delhi University, India
Percentage – 64%

Personal Profile:

Father’s Name : Sh. Munshi Lal
Mother’s Name : Smt. Champa Devi
Nationality : Indian
Religion : Hindu
Gender :
Date of Birth : 19th August, 1981

Declaration:

I hereby confirm that the information given above is true to the best of my knowledge.
Date:
Place: Delhi

[Guest]

hi!
i am jyoti. pursing m.s in vlsi engg and looking for internship.