FlexiOne Pte Ltd : Singapore : Embedded Engineer (USB) : ARM, MIPS, Linux, VXworks, WIN CE

[Admin]

FlexiOne Pte Ltd
http://www.flexione.com

Company Profile
Flexione is a Singapore based Technical Consulting firm and supports large customers in IT , R&D and customised software development. We work with leading multinational organisations in fulfilling their most critical needs in IT and R&D projects.



Experience:
5 - 8 Years
Location:
Singapore ,
Singapore
Education:
UG - B.Tech/B.E. - Any Specialization

PG - M.Tech - Any Specialization
Industry Type:
IT-Software/ Software Services
Functional Area:
Embedded/EDA /VLSI/ASIC/Chip Design
Posted Date:
11 Aug


Job Description
Develop/support embedded software with emphasis on software coding, unit testing & debugging of new products & custom features for specific customer requirements
System analysis & specification with focus on SW architectures & performance reqrmnt


Desired Candidate Profile
5-7 yrs exp. in the area of product devt. or customer support.
SW devt. exp. in C for embedded platforms with processors eg ARM, MIPS & operating systems eg Linux, VxWorks, WinCE
Knowledge of USB protocol & associated device classes an advantage.

Executive Name:
Human Resources

Address:
Not Mentioned

Email Address:
recruit@flexione.com

Telephone:
+65-68733788

Reference ID:
EWE-USB

Keywords: USB, ARM, MIPS, Linux, VXworks, WIN CE

[Guest-IJT]

Name : PATEL MALAV VINODKUMAR
Email : malavpatel01 AT gmail.com
Designation / Skillset : Embedded system,VLSI,Synthesis,Verilog,VHDL,C,C++

Resume :

OBJECTIVE
To secure a challenging position that utilizes my technical and analytical skills and contributes to the overall growth of the organization, and to establish myself as a professional with a keen, innovative thinking and a diligent attitude.

EDUCATIONAL QUALIFICATION
Examination University/
Board Institution Year of Passing % Marks
PG-DIVESD
(Post Graduate Diploma in Integrated VLSI & Embedded System Design)
CDAC-ACTS, Pune
Sunbeam Institute Of Information & Technology, Pune
Feb,2011
61
B.E
( Electronics and Communication Engineering)
Gujarat
University

Kalol Institute of Technology & Research Center
2010
65.43
XII
Gujarat Board
Navarang School,
Ahemedabad

2006
64.40
X
Gujarat Board
Navarang School,
Ahemedabad
2004
72

TECHNICAL SKILLS
Core subject knowledge : Microcontrollers(AVR & ARM), VHDL,Verilog
Basic knowledge of RTOS and Device Driver Programming.
Computer skills
Operating System : UNIX/LINUX internals
Languages : Basic knowledge of C, C++


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More Information about this submission and submitter :-
___________________________________________________
Submission ID : 4384912
Date & Time : 18th Jul 2011 4:56 PM (UTC)
IP Address : 175.100.169.85
Browser Info : Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C)
Predicted Country : --

[Guest]

RESUME
M.BASHEER SHERIFF
E-mail : bsbasheer81 AT gmail.com
_____________________________________________________________
Objective
Looking for challenging position that can effectively utilize my potentials and enable me to grow professionally and personally.
Educational Qualification : M-Tech in Vlsi & Embedded systems
: B.Tech in Electronics and
Communication Engineering
: Diploma in Electronics & Communication Engineering

Computer Skills : Post Graduate in Diploma in
Computer Application.
(P.G.D.C.A) Loyola College, Chennai.
: Advanced Diploma in Hardware &
Networking.
Multimedia : Have experience in the following
Software Adobe Illustrator, Adobe-
Photoshop,Macromedia Flash & Corel
Draw.
Field Experience : Worked as a Designer & Animator in
Advertising Agency named as
Dreamers Ad Media (2yrsExperience).
: Working as a Lecturer in Industrial Control Engineering Dept, in Dr.M.G.R. University,
Chennai -95. (5 years upto till Date).
Subject Handled : Electronics Circuits, Linear & Digital
Integrated Circuits, Principle of
Communication, Transducer
Engineering, Microprocessor & its
Applications, Vlsi Design.
HOBBIES
- Photography
- Surfing in net.
- Listening music, playing cricket.
ACHIEVEMENT
- INSTROM Co-ordinator
- Participated in the training program conducted by National institute of Technical Teacher Training & Research
- Participated in one day workshop on PLC programming
- Participated in one day workshop on BSNL
- Provided training in knowledge transferring the process to the Students Project.
- Arranging the students for Industrial visits.
- To interact the students in Sports activities
Project Done :
DIPLOMA PROJECT :
In the case of emergency television news and reports from a remote area, the video signals of these scenes are often transmitted to the broadcasting station via a satellite contribution link Satellite News Gathering.
We design the mesh reflector antenna in the Ku-band (14—14.5 GHz for uplink and 12.25—12.75 GHz for downlink), and its aperture diameter is 1.5m. We compared antenna configurations of a center-fed type and an offset-fed type. Table 1 shows the result of comparison. The center-fed type is superior in portability because its physical size is smaller than the offset-fed type of same aperture diameter. In addition, the feed horn and sub reflector can be held inside the ribs when the mesh main reflector is folded. The offset-fed type is superior in low side lobe characteristics because of absence of blockage in front of its reflector. The center-fed type is superior in cost effectiveness because the manufacturing cost of symmetric reflector is less than that of asymmetric one. Therefore, we selected a center-fed type.
B.E. PROJECT :
Title : “ FACE RECOGNITION ”
This paper describes a system for face detection and recognition
in an image sequence. Motion information is used to find the moving regions, and probable eye region blobs are extracted by thresholding the image. These blobs reduce the search space for face verification, which is done by template matching. Eigen analysis of edginess representation of face
is used for face recognition. One dimensional processing is used to extract the edginess image of face. Experimental results for face detection show good performance even across orientation and pose variation to a certain extent. The face recognition is carried out by cumulatively summing up the
Euclidean distance between the test face images and the stored database, which shows good discrimination for true and false subjects.
Face detection and recognition are challenging tasks due to variation in illumination, variability in scale, location, orientation (up-right, rotated) and pose (frontal, profile). Facial expression, occlusion and lighting conditions also change the overall appearance of face. Face detection and recognition has many real world applications, like human/ computer interface, surveillance, authentication and video indexing. face recognition system facial components were extracted from the input image and combined into a
single feature vector which was then fed into the recognition classifier. As an alternative, we proposed to train recognition classifiers on each of the components separately and then combine their outputs. Three popular strategies for combining the outputs have been evaluated : voting, sum
of outputs, and product of outputs. We also proposed a new method based on the distribution of the empirical error for weighting the outputs prior to their combination.
M.E. PROJECT :
Title : “SELF-REPAIRABLE RECONFIGURABLE CIRCUIT USING EMBEDDED AUTONOMOUSLY RESTRUCTURING CORES”
Field Programmable Gate Arrays (FPGA) are widely used to implement complex systems. It can be reprogrammed in a system and allows a system using reconfigurable hardware to adapt to changes in external environment. They are used to extend initial capabilities by implementing new functions on the same hardware platform. A FPGA typically consists of a number of configurable logic blocks (CLBs) arranged in rows and columns. Based on the application, some CLBs are activated and other CLBs are kept as spare resources. When any activated CLB becomes faulty, it is possible to repair permanent internal faults in FPGA by using back up circuits. However, this approach becomes complex when the size of the FPGA increases and optimal algorithms need to coexist to make it suitable for online use. In this work, an autonomous restructuring circuit is designed with an objective to reduce the latency, (i.e.) the speed with which the faulty CLBs can be identified and replaced is to be reduced. Also, when any fault
occurs in the active CLB, the fault is rectified using the spare CLB in an autonomous way.
The main objectives of this research work are to provide a repair model for FPGA if any fault is detected. Here, both the permanent and transient faults are detected by using different testing techniques and the faulty CLBs are
Fixed by reprogramming. To develop high speed reliable circuits. To identify the evolved FPGA architecture, structural identification.
make use of spare resources to repair a fault. The drawbacks of the conventional repair strategies in a FPGA are studied and an alternate autonomous restructuring model is proposed. This model reconfigures the FPGA when affected with any permanent or transient faults. In this work, decoding of configuration word and an evolved architecture, fault identification module and autonomous restructuring module are discussed. The proposed autonomous restructuring enables functional recovery for the devices after the occurrence of unavoidable damages and makes the circuit suitable for online. The work has been presented to take care of both single CLB fault and multiple CLB fault.