www.vedaiit.com VEDA Institute of Information Technology Pvt Ltd Hyderabad : VLSI Logical Physical Design Training

[muthukalee]

Name Of The Training Institute : VEDA Institute of Information Technology Pvt Ltd (vedaiit.com)

Location Of The Training Institute : Hyderabad

Training Offered :
VLSI Logical Design
Course Contents
Digital Design
Advanced Digital Design
Contemporary VLSI Design
Verilog language and simulation
Unix Operating System, VI, PERL
Scripting language- PERL
ASIC Synthesis& design constraints
DFT: Scan & JTAG Concepts
Equivalence Checking
Static timing analysis (STA)
Project

VLSI Physical Design
Course Contents
Topics in Digital Design Module
CMOS design concepts
Layout, stick diagrams, reverse Eng
Fabrication
Physical design flow
Floor plan & Power plan
Placement & Optimization
CTS, Routing
Extraction, STA & OCV
Signal Integrity
Power Grid analysis- IR, RJ & EM
DFM
Project

Embedded System Design
Course Contents
Number system & Processor Arthmetics
C and C++
ARM Architecture
Introduction to Embedded OS
DSP Fundamentals
Embedded systems overview
C and C++ lab
ARM lab
Embedded systems lab
Project

Address Of The Training Institute :
VEDA Institute of Information Technology Pvt. Ltd., (VEDA IIT)
4th Floor
Plot No. 90, Road No 2,
Banjara Hills, Hyderabad - 500 034
Andhra Pradesh, INDIA

Website : http://www.vedaiit.com

Email Address: admin@vedait.com

[Guest-IJT]

Name : barnali sarma
Email : barnalisarma011 AT gmail.com
Designation / Skillset : ECE/Fresher/C,C++,Embedded C,Keil C,Assembly Languages 8085/8051,OS,RTOS
I am a 2011 passed out Electronics and Communication Engineer with 74% aggregate in degree.

Resume :

Objective
To be a part of an organization where my knowledge and capabilities can be utilized for achieving common goals and to upgrade my abilities and skills for attaining higher positions in the organization.
Professional Summary.
- Extensive programming experience in C, Embeded C,VHDL,Verilog, ALP
- A strong team player with excellent interpersonal and communication skills and ready to take an independent challenge and has the ability to work in a tea
Academics
Name of the Institution Course Board(or)
University Year of completion Percentage
(%)
Rural Engineering
College, Bhalki
B.E
(ECE) Visveswaraya Technological
University, Belgaum, Karnataka
2011
73.19
Mangaldai Government Higher Secondary School
PUC Assam Higher Secondary
Education Council, Assam
2005
66.67
Mangaldai Town Girls’ Higher Secondary School
10th Board of Secondary Education, Assam
2003
83.33
Project Profile
- Developed a project entitled “entitled “INDUSTRIAL AUTOMATION BASED ON ZIGBEE FOR ELECTRIC POWER GENERATION” (8th sem) at college
- Project Details : In this industry automation system all the machineries are fixed with sensors to capture different parameters and also with security systems. We use single board computers to collect sensor information and send to the master equipment. Master equipment is the server which monitors each industry for different parameters.
- Requirements : Controller, zigbee, power supply module, ADC , sensors, relays, LCD.
Seminar topic : Reliable Physical Layer Network Coding
Achievements
- I got scholarships at district level during schooling
- I was selected in talent search competition at district level during schooling
Extra curricular activities
- I was Active member in “TECHNO UTSAV 2010” – National level Technical festival by Rural Engineering College
- Participated in the ISTE sponsored Two day NATIONAL LEVEL WORKSHOP ON “Challenges in VLSI Design” organized by ECE Department of REC Bhalki .
- Participated in the One day workshop on Fundamentals of HDL organized by ECE Department of REC Bhalki
Hallmarks
- Effective communication skills
- Efficient team leader and team worker – played the role of a leader in the above mentioned project
- Everlasting willingness to learn new things
- Adaptable to any kind of environment and a very fast learner

I hereby declare that details furnished above are true to the best of my knowledge.
Your’s faithfully
Barnali Sarma
-------------------------------------------------------
More Information about this submission and submitter :-
___________________________________________________
Submission ID : 4448836
Date & Time : 5th Aug 2011 12:38 PM (UTC)
IP Address : 115.246.146.182
Browser Info : Mozilla/5.0 (Windows NT 6.1) AppleWebKit/535.1 (KHTML, like Gecko) Chrome/13.0.782.107 Safari/535.1
Predicted Country : India

[Guest]

India's one of the best VLSI Physical Design training institute, Institute of Silicon Systems offering a job oriented training program in VLSI Physical Design (PD) using Cadence tools in Madhapur, Hyderabad.

Course content: Fundamental concepts in Digital Abstraction, MOSFET switch, CMOS basics, Digital Circuit speed, NMOS logic, CMOS logic, combinational logic, sequential logic, synchronous sequential design, timing awareness, setup/hold requirement significance, asynchronous circuits, metastability, synchronization, logic synthesis fundamentals, advanced logic synthesis (PLE based), floor planning, place & route, clock tree synthesis, signal integrity, IR-drop analysis, Static Timing Analysis, low power design techniques etc.. and one mini project, two major projects. (70% of our training goes in doing lab work)

Duration: Full time (8 to 10hr a day) 20 to 22 weeks.

Batch starting on 28th Nov 2011.

Instructors: The course is handled by industry professionals with 17+ yrs of experience.

Prerequisites: B.E/B.Tech in Electrical/Electronics or ME/ M. Tech Electrical/ Electronics/ VLSI/Embedded with min of 65% marks.

Admission criterions: Need to qualify screening test and interview. Test would be conducted in Basic electronics, BJT, FET, CMOS, Digital Electronics, Number systems, logic gates, logic families, combinational ckt, sequential ckt, counters. (All are subjective type questions).

Institute of Silicon Systems
1st Floor, Plot No.11, Shilpi Valley,
Madhapur, Hyderabad.
Landmark: Image hospitals lane.

From registration please visit our website www.siliconsys.in
Thanks,

[Guest]

CURRICULUM VITAE
JYOTHI AMMOURU
Email : jyothi0463 AT gmail.com
To gain employment with a company or institution that offers me a consistently positive atmosphere to learn new technologies and implement them for the betterment of the business.

Degree Institute Board/ University Year Of study Percentage
B.Tech in (Electronics and communication Engg). Aurora’s Engineering college, Bhuvanagiri, Dist.Nalgonda. J.N.T.U 2007-2011 67.18%
Intermediate (MPC) Geethanjali Junior College, Bhuvanagiri, Dist.Nalgonda. B.I.E 2007 85.8%
S.S.C Chaithanya Vidyalaya High School, AzadRoad, Bhuvanagiri, Dist.Nalgonda. S.S.C Board 2005 83.5%
Operating systems : MSDOS, Windows 98, Win9x/2000
Programming languages : C, OOP’s
Application Packages : MS-Office
- Participated in Paper Presentation in Vignan College Of Engineering.
- Active participation in Seminars.
- Participated in 3T-(Trainee to Trainee) program conducted in our college.
- Project : IR Security using Microcontroller
- Organization : Naga Sai Inventive Technologies Private Limited
- Software : keil u Vision2
- Microcontroller : AT89S52
- Components : IR TX & Rx, tsop, LED (IR Led Qed234)
Description :
Now a day’s security is a major problem in all cities. The concept of security is on detection of movement using active sensor to trigger alarm controlled by the microcontroller Intel 8051.
The electrical structure consist of two systems which are the active infrared circuit that used to detect or sense motion and the microcontroller Intel 8051 circuit, used to control the whole operation of the security system. While the software programming is based on microcontroller 8051 instruction set. It contains a program design for a security system as an interaction to operate the electrical structure.
- Project : IMPLEMENTATION OF DISTRIBUTED ARITHMETIC ARCHITECTURE FOR FIR FILTER DESIGN
- Paper :IEEE paper
- Organization : College
- Software : Xilinx
Description :
This Project presents Distributed Arithmetic for highly efficient multiplier less FIR filter design.Furthermore, a modification of the Distributed Arithmetic based on the look up table and filter structure to implement the high-order filter hardware-efficient on FPGA is introduced.
The Proposed filter has been designed and synthesized with ISE 7.1, and implemented with a 4VLX40FF668 FPGA device. Our result shows the proposed Distributed Arithmetic architecture can implement FIR filters with smaller resource usage and similar speed in comparison to the previous Distributed Arithmetic architecture.
- Will power
- Self Motivation
- Confidence
- Patience
I hereby declare that all the information provided above is true and correct to the best of my knowledge.
DATE :
PLACE : BHONGIR
(A.JYOTHI)

[Unregistered]

I am pursuing my b.tech now 4th year i would like to know whether after coaching I will definitely get the job? and what is the coaching payment?