www.sigmaedge.com Software Consulting Pvt Ltd Hyderabad : FPGA Design Engineer

[muthukalee]

Job Title : Design Engineer-II - FPGA

Experience : : 2-4 years experience

Job Descripition
* digital signal processing and applications, RF/Microwave with project work in base band/pass band, or a similar technical field or equivalent related experience.
* ExperienceIf has Bachelor degree, 2 or more years of related experience. If has Ph.D. with thesis in relevant field, no experience required.
* Experience with math intensive blocks implementation viz. Filters, Mixers, Up Converters/Down converters, Modulation/Demodulation schemes, Channel Estimation, etc.
* Experience on 3G/WiMAX/LTE.
* Experience in using multi giga-bit transceivers in FPGAs.
* Knowledge, Skills and AbilitiesEffective verbal and written communication skills that clearly convey information and ideas. Ability to communicate to individuals or groups through a variety of media in a manner that engages the audience and helps them understands the information.
* Ability to use Word, Excel, Microsoft Project and Visio software programs, to a level of professional proficiency. Able to produce professional Engineering reports including introductions, conclusions and recommendations.
* Ability to analyze and resolve technical problems of a moderate complexity quickly and independently
* Working knowledge of programming languages including C/C++, Visual Basic and structured programming techniques and/or knowledge of FPGA programming language, techniques and tools.
* Basic knowledge of electronic design.
* Knowledge of simulators, ICE debuggers and Integrated Development Environments and/or FPGA simulators and functions.
* Competent RF and/or Digital lab skills
* Ability to self-manage technical design activities from concept to validation including and test plan and methodology.
* Working knowledge of communication theory.
* Ability to use MATLAB, Quartus – II/ Xilinx ISE, Timing Analyzer tools.
* Ability to code using VHDL/Verilog.
* Ability to apply Engineering Mathematics concepts (Linear Algebra, Probability.)
* Knowledge of high end FPGA architectures.

Contact us:
Sigmaedge Software Consulting (P) Ltd
9-1-127/3, 43 Sarojini Devi Road
Secunderabad - 500 003 AP India
careers@sigmaedge.com
http://www.sigmaedge.com

[Guest-IJT]

Name : Mohamed ameerjan.k
Email : mohamed.amirjan459 AT gmail.com
Designation / Skillset :

Resume :
MOHAMED AMEERJAN.K
OBJECTIVE :
To obtain an excellent career in the industry and be in a good position in developing organization, which gives me an opportunity to showing all my skills practically with hard work and dedication.
STRENGTH :
Ability to work in team
Ability to work as an individual
Accurate in work fast
Hard working and good work
EDUCATIONAL QUALIFICATION :

Exam passed Name of the Institution Year of passing Percentage
B.E PET Engineering College,Vallioor 2007-2011 67%
HSC Nehru Vidhya Salai Hr.Sec.School,Madurai 2006-2007 81.9%
SSLC Nehru Vidhya Salai Hr.Sec.School,Madurai 2004-2005 88.4%

PROJECT :
FPGA DESIGN FOR MULTI-FILTERNG TECHNIQUES USING FLAG-BIT AND FLICKER CLOCK
Real time systems typically suffer from delay in data processing. This delay is caused by many reasons such as computational power, Processor unit architecture and synchronization signals in these systems. In order to increase the processing power. A new architecture and clocking technique is carried out in this paper hence the performance. This new architecture design called Embedded Parallel Systolic Filters (EPSF) would process data gathered from sensors and landmarks using high architecture and bit-flag with a flicker clock perform significantly better in multiple input sensors signals under both continuous and interrupted conditions. Unlike the usual processing units in previous tracking and navigation systems used in robots, this system allows autonomous control of the robot through multiple techniques of filtering and processing strategy. Further more, it also offers a speedy performance that minimizing the delay about 50%.
SOFT SKILLS :
SKILL SET
Programming Languages : c, c++
Packages : Ms office
Windows : Windows 98/2000/xp

ACHIVEMENTS :
I finished English type writing in first class
I got third place in Tamil in HSC examination
I was member in JRC , attended many camps and completed it successfully
AREA OF INTEREST :
Electron devices and circuits
Antenna and wave propagation

HOBBIES :
Listening music, watching movies, reading books
Travelling and making friends
DECLARATION :
I do here by declare that all the above statements made in this resume are true, complete and correct to the best of my knowledge and belief.
Place: Chennai Yours sincerely,
Date : 19.06.2011.
MOHAMED AMEERJAN.K
-------------------------------------------------------
More Information about this submission and submitter:-
___________________________________________________
Submission ID : 4272916
Date & Time : 19th Jun 2011 2:09 PM (UTC)
IP Address : 117.193.171.130
Browser Info : Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; BTRS7181; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0)
Predicted Country : India

[Guest]

CURRICULUM VITAE
S.Shashi kiran,
Email ID : shashi.sabadu AT gmail.com

.
CAREER OBJECTIVE
To prove myself dedicated worth full and energetic in a progressive organization that gives me scope to apply my creative thoughts and skills and be a member of a team that dynamically works towards organizational and personal growth.
ACADEMIC PROFILE
- S.S.C from Board of Secondary Education, Andhra Pradesh, 2004 with 84.33%.
- Intermediate from Board of Intermediate Education, Andhra Pradesh, 2006 with 90.1%.
- B.Tech in Electronics & Communication Engineering, from Jawaharlal Nehru Technological University, 2010 with 65%.
- Completed P.G.Diploma(VLSI) course in Vector india
SKILL EXPOSURE
HDLs : VHDL and Verilog
Simulation : Modelsim
Synthesis : Xilinx (XST)
DFT Tools : DFT Advisor
Placing and routing : Xilinx-ISE
Physical Verification : Calibra
Operating System : Win Xp, Win 2000, LINUX.
STRENGTHS
- Self-Motivation, Self-Confidence and Quick Learner.
- Emerging New Technology, Good listener.
- Capable of coming up with own initiative to carryout individual task and equally adoptable to the situation of working in a group.
PROJECT EXPERIENCE
PROJECT : 1
Title : “Digital Alarm Clock”
Environment : VLSI
Description :
I did Digital Alarm Clock by taking the input signals Clock, Reset, load time, set hours, set minutes, seconds, set_AM_PM, Load Alm, Alarm Hours In, Alarm Mins In, Alarm_AM_PM_In, Alarm Enable. The Alarm output should go high when the current value of time equal to alarm time. The alarm should stay on until either the Alarm Enable signal goes low, which equates to turning the alarm off, or after period of 1 minute has elapsed when left on. If power is lost, and then powered up again, it should display the time 00 :00:00 and ‘Flashing’ signal should be activated high. This causes the display to flash and so indicate that the alarm clocks time needs to be set. The Flashing signal should stay high and the clock’s time should increased from zero until a new time is set.

PROJECT : 2
Title : “Modulation and Demodulation by using
QPSK in MATLAB”
Client : EdwareUK Ltd, Hyderabad
Environment : MATLAB
Team Size : 4
Description :
I have done the modulation and demodulation of Quadrature Phase Shift Keying by considering image as a real time example. The converted data bits of an image are applied to Quadrature Phase Shift Keying modulator. Add White Gaussian Noise is applied for better performance to the Quadrature Phase Shift Keying modulated waveform, while it is carried through a channel. At the receiver end, Quadrature Phase Shift Keying demodulator demodulates the obtained modulated signal to regain the digital data and the corresponding digital data is further converted into an original image. Hence I conclude QPSK modulation is low cost, high efficiency and is mainly used in designing of “Wireless Modems”.
AWARDS AND ACCOMPLISHMENTS
- I have participated in College games and got many prizes.
- I have Got Many Prizes in School level.
- I have got many prizes in paper presentations.

[Guest]

I am M. Shivani not yet completed my MBA Persuing can i work in ur office as a HR operator, mine one sem is in pending, i am thinking to work so as to gain some knowledge about HR process and earn money, my Residence is Kavadiguda, hyd now MBA HR continuing.