FPGA Design Engineer : Resume CV

[udayraj_mp]

UDAYRAJ MP
E-mail : mp.udayraj AT gmail.com , mp.udayraj AT digirati-systems.net

OBJECTIVE :
To seek challenging opportunities in a leading technology industry and contribute to the growth and success of the organization and at the same time help me with the best of learning opportunities to enhance not only my technical skills but also my character and personality at large.

PROFESSIONAL EXPERIENCE :
DESIGN ENGINEER having 3 years of experience working on FPGA based designs.

Current employer : DIGERATTI SYSTEMS
Designation : Design engineer
Department : FPGA
Period : MAY 2007 – Till date
Location : BANGALORE

TECHNICAL SKILL SET :
- Hardware Description Language : VHDL, VERILOG
- EDA Tool : Xilinx ISE 9.1i, Chipscope Pro analyzer
- Simulation tool : Modelsim
- Operating System : Windows 95/98/2000/XP
- Programming Language : Basic knowledge of .net (asp.net, vb.net), C, C++
- Hands on experience in development of FPGA (RTL design), developing behavioral models and simulation level testing.
- Hands on experience in using Xilinx FPGA and tools.

EDUCATIONAL QUALIFICATIONS :
Year of completion Course and Institution :
2006 Bachelor of Engineering(BE) : Telecommunication
Institution : Sir M Visvesvaraya Institute Of technology (SIR MVIT),
Affiliated to VTU(Visveshwaraiah Technological University)
Location : Bangalore
2002 2nd PUC(10 + 2)
Institution : Seshadripuram Composite Pre-University College
Location : Bangalore
2000 10thStandard
Institution : Seshadripuram Boys High School
Location : Bangalore

PROJECTS CARRIED OUT :
I. IP CORE DEVEOPMENT OF SPARTAN-3E FPGA BASED MIL-STD-1553 PROTOCOL
CONTROLLER COMPATIBLE WITH DDR SDRAM
Team size : Self
Role : RTL HARDWARE CODING USING VHDL, SYNTHESIZING and ANALYZING.
Tool : Xilinx ISE 9.1i, chipcsope pro analyzer, Modelsim
Abstract :
Mil-Std-1553B data bus protocol being implemented on SPARTAN-3E FPGA that can provide interfaces to Avionic bus called MIL-STD-1553B.Dual channel Mil-Std-1553B protocol based interface board provides an interface between ISA bus and dual redundant Mil-Std-1553B bus. The Controller to provide 1553B interface implements all three of the MIL-STD-1553B functions Viz., as Bus Controller, Remote Terminal(31 RT), and Bus Monitor.
Tasks involved :
- Developed the modules for
(i) Bus Controller : There is only one Bus Controller at a time on any MIL-STD- 1553 bus. It initiates all message communication over the bus.
(i) Remote Terminal(RT) : The function of the RT is to respond to the commands issued by the Bus Controller.The design consists of 31 RT’s .
(iii) Bus Monitor : A Bus Monitor cannot transmit messages over the data bus. It primary role is to monitor and record bus transactions, without interfering with the operation of the Bus Controller or the Remote Terminals.
(iv)DDR SDRAM INTERFACE : It interfaces with the DDR SDRAM memory with 16 bit host interface and controller. It performs read and write access based on the host and controller requests.
- Developed the modules for Memory Management and Host Processor Interface
- Integrating all the modules for the complete development of IP core.

II. IP CORE DEVELOPMENT OF ARINC 429 CONTROLLER
Team size : Self
Role : RTL HARDWARE CODING USING VHDL, SYNTHESIZING and ANALYZING.
Tool : Xilinx ISE 9.1i, chipcsope pro analyzer, Modelsim
Abstract :
ARINC 429 controller being implemented on FPGA that can provide interfaces to Avionic bus called an ARINC 429 data bus a specification, which defines how avionics equipment and systems should communicate with each other.ARINC 429 employs a unidirectional data bus standard known as Mark 33 Digital Information Transfer System (DITS). Messages are transmitted at a bit rate of either 12.5 or 100 kilobits per second to other system elements, which are monitoring the bus messages.
Tasks involved :
- Developed the modules for the ARINC 429 CONTROLLER and Host Processor Interface

III. IP CORE DEVEOPMENT OF SPARTAN-2 FPGA BASED MIL-STD-1553 PROTOCOL CONTROLLER COMPATIBLE WITH STATIC RAM
Team size : Self
Role : RTL HARDWARE CODING USING VHDL, SYNTHESIZING and ANALYZING.
Tool : Xilinx ISE 9.1i, chipcsope pro analyzer, Modelsim
Abstract :
Mil-Std-1553B data bus protocol being implemented on SPARTAN-2 FPGA that can provide interfaces to Avionic bus called MIL-STD-1553B. Dual channel Mil-Std-1553B protocol based interface board provides an interface between PCI bus and dual redundant Mil-Std-1553B bus. The Controller to provide 1553B interface implements all three of the MIL-STD-1553B functions Viz., as Bus Controller, Remote Terminal, and Bus Monitor.
Tasks involved :
- Developed the modules for
(i) Bus Controller : There is only one Bus Controller at a time on any MIL- STD- 1553 bus. It initiates all message communication over the bus.
(i) Remote Terminal(RT) : The function of the RT is to respond to the commands issued by the Bus Controller.
(iii) Bus Monitor : A Bus Monitor cannot transmit messages over the data bus. It primary role is to monitor and record bus transactions, without interfering with the operation of the Bus Controller or the Remote Terminals.
(iv) RAM INTERFACE : It interfaces with the STATIC RAM memory with 16 bit host interface and controller. It performs read and write access
based on the host and controller requests.
- Developed the modules Host Processor Interface
- Integrating all the modules for the complete development of IP core.

RESPONSIBILITY :
- RTL Hardware designing using VHDL.
- SYNTHESIZING the modules using Xilinx ISE 9.1i synthesizer tool.
- Verifying the modules by writing a test bench for the modules using MODELSIM simulator.
- ANALYZING (Verifying) the modules using Chipcsope pro analyzer.

PERSONAL DETAILS
Date of Birth : 04 - 05 -1984
Gender : Male
Marital Status : Single
Languages Known : Kannada, English and Hindi
Other Interests : Cricket, Taekwondo, chess, Movies, Music.

Place : Bangalore.
Date : UDAYRAJ M P

[Guest]

Hello Sir

Can you help me regarding the 1553 core tat u have mentioned in your cv. i am an engineering student and have been assigned a task to design it..

looking to your reply