FPGA Design Engineer Bangalore : www.waveaxis.com Technologies Pvt Ltd

[radhaj]

Sr.FPGA Design Engineer
waveaxis.com

Job Description : Design of FPGA Hardware for a variety of markets. .

Candidate Profile : MTech /B.E/ B.Tech/MSc Electronics with minimum 4 Years Experience in FPGA Design.

Key Skills :
• Expertise in VHDL/vERILOG RTL Coding, SystemC/System Verilog.
• C/C++, PCB Designing, EDA tools expertise.
• Extensive Expertise FPGA Synthesis and PAR Tools
• Skill sets - FPGA, Verilog, VHDL, RTL, Synthesis

Minimum Experience : 4 years

Location : Karnataka - Bangalore

About us :
Waveaxis delivers LCD based Automotive Instrument Cluster
Waveaxis technologies Pvt. Ltd has successfully designed from scratch and delivered a LCD based automotive instrument cluster for a major Indian automotive OEM.

CONTACT US:
#4, 3rd Floor, K.R.Garden,
5th Main, 8th Block, Koramangala,
Bangalore - 560095, India
Tel : +91.80.41308070
http://www.waveaxis.com/Careers.html
http://www.waveaxis.com

[Guest]

Hello Sir/Madam,
I am B.P.Nanda, BE graduate in the field of Electronics and Communication from Visvesvaraya Technological University,Belguam (Karnataka) . I have pasted my resume.
Kindly do look into it and respond.
Thanking you,
B.P.Nanda
B.P. Nanda #103, Venkataswamy E-mail : nandabp28 AT yahoo.com Reddy Layout, 8th block, Cell: +91-9972097589 Koramangala, Bangalore, KA-560095

Objective :
To excel my aim and talent in the field of Engineering. I am a B.E. (Electronics and Communication) Engineer. Hard-working, punctual, sincere and ready to work under stress are some of the assets that I posses.
Educational Qualification :
Institution Stream University Year of passing Percentage
East point college of Engineering & Technology, Bangalore, KA
Electronics
and Communication
Visvesvaraya Technological University
(VTU)
2010 Semester %
1 63.35
2 70.97
3 64.00
4 60.00
5 58.44
6 57.33
7 63.11
8 75.20

Average
64.05
St. Francis composite P.U college, Bangalore, KA

PCME
Pre-University Certificate
(PUC)

2006
78.50
ASC public school, Bangalore, KA
General subjects

Central Board of Secondary Education
(CBSE)

2004
56.20
Technical Skills :
- Basic programming in C, C++.
- Assembly level Programming in Microcontroller-8051 and Microprocessor-8086.
- Cadence (Assura and Virtuso).
- VHDL/Verilog (using Xilinx ISE 10.1 and 7.1i tool).
- MATlab (7.1/6.0).
- Microsoft Word, Excel, PowerPoint, outlook.
- MASM (DOS platform).
- Keil.
Project Details :
Work place : NxG Semiconductors, Bangalore, KA Feb, 2010 to Jun, 2010
Team size : 4
Tools : Xilinx ISE 10.1 and 7.1i
Hardware Description Language : Verilog
Simulators : Modelsim simulator 5.7g
Responsibilities : Designing the architecture, Developed codes, RTL design, FPGA Implementation, performed optimization in terms of area, Power and time.
Reference : IEEE papers.
Purpose : Final Semester Project.
Title : Implementation of 2D-DA DWT/IDWT architecture on FPGA for image compression.
- Image compression is an integral part of any image processing unit. Compression of image is based on JPEG 2000 standards. JPEG 2000 recommends use of wavelets and encoding schemes for compression.
- DWT is the most time consuming unit and is also very intensive mathematics, and consumes large power due to large number of arithmetic operations. Multipliers and adders are the major arithmetic units of a DWT processor.
- Implementation of DWT on Field Programmable Gate Arrays is one of the most challenging activities that are addressed by many of the research activities.
- As the hardware resources on FPGA are limited, it is required to optimize the DWT architecture, so that it consumes limited number of slices and also operates at very high frequency.
- In this current project, Distributive Arithmetic (DA) based DWT architecture is modified.
- The DA architecture is modified by splitting the existing LUT’s into two parts, and splitting the inputs into even and odd terms. This introduces parallelism in the DA architecture and hence the speed is increased.
- Mat lab reference model is developed and validated with different images. HDL models are developed for the modified DA architecture and are implemented on FPGA.
- DWT architecture implemented on FPGA is verified by interfacing memory and VGA controller for input and output display.
- The modified DA results are compared with basic DWT results with respect to speed and area.
Seminar :
- MPLS Traffic Engineering.
Employment History :
ONS Search, Bangalore, KA Oct, 2010 to present
Recruiter
- Sourced resume for Semiconductor industry; mainly on ASIC/VLSI Design/Verification.
- Made phone calls to candidates within India in order to perform Staffing on behalf of clients.
Adea International Pvt Ltd., Bangalore, KA Sep, 2010 to Oct, 2010
Technical Recruiter (managed staffing)
- Performed staffing for various US companies.
- Sourced resume and made phone calls to interview candidates and submit them to the client.
- Made use of Excel to keep a track of the status of the candidate regarding submission or non submission to the client.
Achievement
- Received award of Rajya Puraskar in Bharat Scouts and Guides.
Hobbies
- Collecting technological information.
- Playing chess and basketball
- Watching horror movies.
- Drawing.
Personal Information
Name : B.P. Nanda Father Name : B.P. Partha Mother Name : M.K. Neelavathi Date of birth : 28.01.1989 Gender : Male Nationality : Indian

[Unregistered]

Do I get a internship in your company?