QualCore Logic Ltd Hyderabad : Analog Engineer

[muthukalee]

Analog Engineers (Code: IN107)

Qualification :M. Tech / M. E. in Electrical Engineering, B. E. / B. Tech

Experience :3-5 yrs as mixed-signal/analog circuit designer

Key Skills : CMOS Circuit Design, CMOS Device Physics, Circuit Simulation

Responsibilities :
Design and Development of custom and standard-compliant analog IPs like PLLs, DLLs, High Speed IOs like LVDS, High-Speed Links, ADC/DACs, Voltage Reference Generators etc.
Create schematics; assist with circuit layout
Simulate test chip circuits and evolve/enhance circuit design

Requirements :
Familiar with Cadence design tools
Should have proven success in bringing circuits to high volume manufacture
The candidate must have strong mixed-signal and high speed, low power analog CMOS / Bi-CMOS design concepts and skills with a solid understanding of transistor physics
Should have strong comprehension of circuit design & prior exposure with fabrication process
Should have been involved in 2-3 tape-outs of analog ICs

Location : Hyderabad, India

Please send your resume to hr@qualcorelogic.com

About us :
QualCore Logic is the recognized leader of silicon-proven Analog, Mixed-signal and Digital intellectual property (IP) for system-on-chip (SoC) designs for the past 15 years. QualCore’s IP portfolio includes high performance PHYs (DDRs, SerDes etc.), ADCs, DACs, PLLs, DLLs, Special IO’s, Power Management Solutions and various Analog and Digital building blocks.

Contact us :
QualCore Logic Ltd.
7-145 Nagendra Nagar,
Habsiguda,
Hyderabad - 500 007
India
http://www.qualcorelogic.com

[Guest-IJT]

CURRICULUM VITAE
M.GOPI KUMAR
EMAIL : gkumar509 AT gmail.com

Personal Details :
NAME : M.GOPI KUMAR
FATHER’S NAME : M. HANUMANT RAO
DATE OF BIRTH : 7th march 1989
SEX : male
NATIONALITY : Indian
MARITIAL : Single

ACADEMIC QUALIFICATION :
EXAMINATIONS BOARD / UNIVERSITY SCHOOL / COLLEGE YEAR OF PASSING :
Secondary Examination W.B.B.S.E Sanghamitra Vidyalaya 2006
Higher Secondary Examination NIOS Heritage Pursuing

PROFESSIONAL QUALIFICATION:
INSTITUTES NAME COURSE PERCENTAGE DURATION
THE GEORGE TELEGRAPH TRAINING INSTITUTE CIVIL DRAUGHTS MAN SHIP WITH AUTO CAD 72.59 % 12 MONTHS

EXTRA QUALIFICATION : Basic Computer

LANGUAGES KNOWN : English, Bengali, Hindi & Telgu

HOBBIES : Meditation, playing cricket.

DATE:
Signature

[Unregistered]

Amulya Bai.N
amulya1120 AT gmail.com

PROFESSIONAL OBJECTIVE :
To work in challenging and competitive environment

PROFESSIONAL TRAINING :
An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from Institute of Silicon Systems Pvt Ltd., Hyderabad

COURSE OUTLINE :
VLSI Fundamentals, CMOS Basics, Digital Design Floor Planning, Power Planning, Placement and Routing, clock tree synthesis, static timing analysis timing optimization, cross talk analysis, IR Drop Analysis and Physical Verification.

Tools :
Experience in physical design of 130nm and 90nm technologies using Cadence tool
Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis
Encounter Timing System –Static Timing Analysis and Crosstalk Analysis
RTL Compiler- Logic Synthesis
Assura – Physical Verification
Virtuoso-Layouts Design

ACADEMIC EDUCATION :
Graduate in Electronics & Communication Engineering from Hyderabad City,Andhra Pradesh,INDIA in 2011
Pre-Graduation study is from a Mini-town,Guntakal,Anantapur Dt., Andhra Pradesh,INDIA

SOFTWARE EXPOSURE :
EDA tool :Cadence,Modelsim,xilinx ISE 9.2
Operating system :Windows, Unix
Languages :C, VHDL.
Scripting Languages :TCL (Basics)
Domain :ASIC\FPGA Design flow,
Digital design methodologies
Knowledge :RTL coding,simulation,synthesis

VLSI PROJECTS :
LOGIC SYNTHESIS
Project 1 :
8-Bit synchronous counter with an asynchronous Reset.
Clocks/Frequency : 2/200MHz
Role : Generated Constraint file, TCL file, Performed Wireload and ZeroWireload model.

Project 2 :
256-bit counter
Role : Calculated the Clock Frequency, Generated Constraint file, TCL file, Performed Wireload and ZeroWireload model.

LAYOUTS :
Designed Layouts for Basic gates like Inverter, NAND, NOR using Folding Technique.

PHYSICAL DESIGN :
Project 1 : PCI-DATA (TOP LEVEL)
Tools : SOC Encounter, ETS.
Gate count : 22,000
Blocks /Cells /IOs :12/26640/120
No. of Clocks : 7
Frequency :150 MHz
Technology : UMC 0.18 micron
Role : Performing sanity check , Design import , Floor Plan , Power Plan , Placement , Trail Route , Power Analysis , Timing analysis , CTS .

Project 2 : Brx-Top (BLOCK LEVEL)
Tools : SOC Encounter, ETS.
Gate count : 12,000
No. of Clocks : 3
Frequency : 333 MHz
Technology : UMC 0.18 micron
Role : Performing sanity check, Design import, Floor Plan, Power Plan, Placement, Trail Route, Power Analysis, Timing analysis Problems Observed when metal stripes and rings are laid at lower metal layers.

Project 3 :
Objective :Timing Driven Layout
Tools :SOC Encounter, ETS.
Gate count/Area :3,10,736/ 1582334.9 um^2
Macros /STD Cells :12/28703
No. of Clocks :17
Frequency :200MHz
Technology/Layers : TSMC 0.13 micron/5 Metal Layers
Role : Performing sanity check, Design import, Floor Plan, Placement, Trail Route, Power Analysis, Timing analysis, CTS, Detailed Routing.

B-TECH PROJECT :
Implementation of pi/4 QPSK modulator and demodulator on spartan-3E FPGA :

Aim :
The main aim of this project is to implement pi/4 QPSK modulator and demodulator on spartan-3E FPGA for mobile applications

Tools :
HDL :VHDL
EDA Tools :Modelsim,Xilinx ISE9.2

Implementation Plan :
The program code is developed in VHDL.
The code is dumped in FPGA kit.
Simulation and Synthesizing is done by using XILINX ISE 9.2i tool.

[Unregistered]

Kishore Roy
kishoreroy222 AT gmail.com

Dear Hiring Manager,
Please accept my profile for job in your organization. My background and skills in Electronics Engineering/ VLSI Design will prove to be an effective match for your qualifications.

I have a Bachelor degree in Electronics Engineering with 81%.and M.Tech in VLSI Design from National Institute of Technology Nagpur with 8.96 CGPA and qualified GATE with 99.52 percentile.

I am looking forward to make my career in semiconductor industry. During my education I got Muster basics of VHDL,Verilog HDL, C,C++, Cadence Virtuoso, EDA tools (ModelSim, Spice NGSpice, Xilinx ISE), MATLAB , Linux, CMOS design, Digital circuit design, Memory Characterization (basics),Analog Circuit Design.

I look forward to discuss my qualifications further and can be reached by email at kishoreroy222 AT gmail.com.

Thank you so much for your time.
Best,
Kishore Roy