EDA Development Engineer Noida : www.atrenta.com Pvt Ltd

[muthukalee]

atrenta.com

Senior Software Engineer- Low Power
Location : Noida, India
Department : Engineering

Job Details :
Job needs understanding and development of EDA tools using latest
software techniques. Integration with team and good communications skills are also
required.

Academic Qualification
B.E / B.Tech/ M. Tech. in Computer Science/ Electrical Electronics Engineering from reputed Universities, preferably IITs.

Experience : 2 to 4 years of relevant experience

Position Responsibilities
Design and development of state of the art EDA tools involving development in one or more of the following areas :- developing new and innovative algorithms in the area of power reduction and estimation.

Skills Required
- Strong knowledge of C/C++ on UNIX.
- Familiarity with ASIC design flow and the EDA tools and methodologies used therein. In-depth knowledge of Verilog/VHDL semantics from simulation and synthesis perspectives, and power reduction and estimation techniques.
- Knowledge of EDA power tools in will be a plus.
- Excellent algorithm analysis skills and a good knowledge of data structures.
- Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success

Reference Code : Low Power

About us :
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation.

Contact us :
Atrenta (I) Pvt. Ltd.
A-9, Sector 4,
Noida, 201 301, UP
India
Tel: +91-120-309-7800
Fax: +91-120-253-6180
HR - info@noida.atrenta.com
http://www.atrenta.com

[Guest-IJT]

Name : Selvi.M
Email : arpudhaselvi123 AT gmail.com
Designation / Skillset : Fresher Electronics Communication Engineer
I finished my final year M.E (Communication and Networking) with 71.9 % of aggregate in Madras Institute of Technology campus, Anna University, Chennai. I would like to apply for the post of Fresher Electronics Communication Engineer. I firmly believe that I will be a good fit in this innovative environment. I have enclosed my curriculum vitae. Thank you for your time and consideration.

Resume :
SELVI.M
OBJECTIVE
Looking forward to associate myself with an organization where there is an opportunity to share, contribute and upgrade my knowledge for the development self and organization served while being resourceful, innovative and flexible.
EDUCATION
1. Completed M.E. under the department of COMMUNICATION AND NETWORKING ENGINEERING at MADRAS INSTITUTE OF TECHNOLOGY, Anna University Chennai in the year 2011. Percentage Obtained : 71.9 %
2. Completed B.E. under the department of E.C.E. at P.T.Lee Chengalvaraya Naicker College of Engineering and Technology, Kancheepuram in the year 2009. Affiliated to Anna University. Percentage Obtained : 71 %
3. Completed XIIth at S.K.D.J. Higher Secondary School with an aggregate of 58% in the year 2005.
4. Completed Xth at S.K.D.J. Higher Secondary School with an aggregate of 66% in the year 2003.
CERTIFICATIONS
1. Attended National Workshop on “NEXT GENERATION WIRELESS TECHNOLOGIES – LONG TERM EVOLUTION (NGWT-LTE)” at MIT.
2. Attended National Seminar on “Research Challenges in Wireless Sensor Networks (RCWSN)” at MIT.
3. Completed CCNA Exploration : Network Fundamentals, Routing Protocols and Concepts at MIT.
4. Completed “7 days programme on JAVA” at MIT campus, Anna University, Chennai-44.
5. Training done under the field of AC Coaches Maintenance related to Electronics Circuits at Southern Railway.
AREA OF INTEREST
1. Digital Signal Processing
2. Optical communication
3. Digital Electronics
PROFESSIONAL QUALIFICATIONS
1. Languages : C & Java beginner
2. Operating System : Windows XP, 7
3. Software : Matlab
PROJECT DETAILS
Project Title : Design of lattice form optical delay line filter using constrained least square method (Phase II- M.E.).
Description : This project deals with Optical delay line filters are used in optical communication for Broadband application. It presents a method for analyzing a lattice form optical delay line filter using constrained least square method with N stages. This project can be applied to WDM, FDM communication system, Dispersion Equalizer, Adaptive Gain Equalizer. More over the signal suppression is done in this project. Signal suppression is desirable to transmit Optical Carrier Suppressed for more flexible application in future Broadband access networks.
Project Title : Design of a multichannel lattice-form optical delay line (Phase I- M.E.).
Description : This project deals with one-input M-output (1×M) circuit configuration and a synthesis algorithm for realizing an optical finite impulse response (FIR) lattice filter having M output channels (M=2). This circuit configuration has a multilayer structure consisting of multiple Mach-Zehnder interferometers with delay time differences of zeros. Two kinds of five-channel interleave filters are demonstrated as synthesized example: one has a flat group delay response while the other has an inclined group delay response.
Project Title : Airport signal light monitoring system using microcontroller (B.E.).
Description : This project deals Airport signal light monitoring system using microcontroller for flight take off purpose. In the airport, the control room gives the clearance signal to the Air Traffic Controller (ATC) through walkie-talkie at the time of flight take off. This process consumes more time for communication, it can be overcomes by using this project. In this project, strobe lamp is placed at the runway. The clearance signal from the control room is given to the strobe lamp. The microcontroller controls the illumination of dedicated LED and LCD display to indicate each status of the strobe lamps.
PAPER ACCEPTANCE
“Design of lattice form optical delay line filter using constrained least square method” has been accepted in the International Conference on Recent Trends in Information Technology (ICRTIT) 2011 conference proceedings at M.I.T., Chrompet,Chennai-44.
PERSONAL STRENGTHS
1. Ability to grasp & learn new technologies.
2. Willing to take additional responsibility.
3. Determined to go that extra mile to gain perfection.
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More Information about this submission and submitter :-
___________________________________________________
Submission ID : 4357081
Date & Time : 11th Jul 2011 9:16 AM (UTC)
IP Address : 223.177.198.39
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