www.vegaglobal.com VEGA GLOBAL EDUCATION CHENNAI : Oracle Web Logic Portal , UCM, IDM TRAINER

[mskavi]

VEGA GLOBAL EDUCATION CHENNAI : TRAINER
Company Name : VEGA GLOBAL EDUCATION ( vegaglobal.com )
Company Location : CHENNAI
Designation (of vacancy) : TRAINER
Company E-mail ID : john@vegaglobal.in
Company Website : www.vegaglobal.com

Job Description, Candidate Profile, Company Profile, Company Address :
TRAINER in Oracle Web Logic Portal , UCM and IDM
Oracle Web Logic Portal , UCM and IDM

Module :
TOC

Getting Started :
• Explain Core features of the WLP, UCM and IDM
• Explain the integration among the above mentioned products

Getting Started with WebLogic Portal (WLP) :
• Describe the business objectives associated with enterprise portals
• List the components of the WebLogic Platform
• Configure a development server

Portal Design, Configuration, Look and Feel Development (WLP) :
• Assemble a portal desktop using Workshop for WebLogic
• Define menus using books and pages
• Configure and position portlets on a desktop
• Describe the components of Oracle UCM look and feel framework
• Develop portal skeletons and shells (High Level)
• Develop portal skins and themes(High Level)
• Extend skins using genes and chromosomes (High Level)
• Develop page layouts
• Explain the fundamentals of Web service communication and development
• Administration fundamentals

Content Management - UCM :
• Describe the architecture of UCM and Content Repository
• Classify and organize content using types
• Develop and publish content according to a workflow
• Surface content in a portal using selectors and placeholders
• Use APIs to access and manage content
• Discuss techniques used to access 3rd party content management systems

IDM :
Single Sign On and Web Access Control
Content Access Control
Identity Administration
Identity Governance
Federated Identity
Fraud Detection
Directory Services
Authentication
Security Tool Kit
Web Services Security

SALARY IS NOT THE CONSTRAIN FOR THE RIGHT CANDIDATE

DESIRED CANDIDATE PLEASE DO CONDUCT :
JULIUS HR
9943822674

[Guest-IJT]

Name : adarsh k s
Email : adru2008 AT gmail.com
Designation / Skillset : vhdl/verilog
I am Adarsh k.s, completed Master of Engineering in VLSI Design stream from PSNA College of Engineering &Technology ,Dindigul. which is affiliated to Anna University.I am interested in exploring the possibility of seeking employment with your organization. Please find my resume enclosed, it will furnish you with the details relevant to my knowledge, skills and education. References and any other information you require shall be promptly provided upon your request.

Resume :

Profile - A challenging determined Post-graduate (M.E) in VLSI Design with good communication skill and ready to work both independently and as a member of a team, utilizing the skills acquired during my course and experience..
Career Objective - To associate with an organization utilizing the skills, abilities and knowledge, to grow in a professionally competitive environment so as to implement & practice what I acquired over the years.
Academic Qualifications :
Degree / Qualification Year of Passing Percentage
M.E(VLSI Design) [Anna University] 2009 71%
BE(ECE) [Anna University] 2007 67%
HSC [Public Examination Board] 2003 68%
SSLC [Public Examination Board] 2001 74%
Experience
- 2 years experience as a lecturer in the Engineering college
Industrial Exposure
- Undergone an implant training in KELTRON
Technical Details :
- MS DOS, Windows
- C,C++, Verilog ,VHDL, OrCAD
Achievements
- Attended a 1 day workshop in recent trends MEMS Technology
- Member in ISTE
- Presented a paper in National conference
Project Details :
P.G PROJECT
Project : A Novel Implementation of Fault-Tolerant Crypto Processor
using Dynamic Reconfiguration.
HDLs : VHDL
Tools used : Modelsim, Xilinx ISE
Project Type : FPGA Xilinx vertex2
Work done : Coding, Integration with other modules, simulation
Team size : 1
Place : PSNACET, Dindigul, Tamilnadu.
Duration : 6 months
Functional Description
In this project it is desired to implement the realization of a fault tolerance technique for a dynamically reconfigurable array of programmable cells. The three parts of the technique are fault detection, fault reconfiguration, and fault recovery. A prototype was developed implementing fault detection, fault reconfiguration, and check pointing and rollback in a fine-grained FPGA-like structure. Simulations of the HDL model of the described FPGA prototype including the reconfiguration control unit, fault detection, and rollback hardware show the excellent performance of the concept. Writing test-bench with test cases and simulating the code. Synthesized above design using Xilinx ISE. The technological development towards nanoscale feature sizes and the growing influence of deep-sub micrometer effects will result in an inherent unreliability of the individual components of future circuit implementations and a higher vulnerability towards external influences.
U.G PROJECT
Project : Implementation of Unicast/Multicast/Broadcast Communication in ARM platform using LINUX
Tools used : Linux OS, C
Work done : Coding.
Project Type : Communication
Team Size : 4
Industry : CDAC, Trivandrum. Kerala
Duration : Feb 2007-Mar 2007
Functional Description
This project deals with the program for implementing Unicast/Multicast/Broadcast communication in PRAYOG BOARD .This is an ARM platform developed by CDAC for their software development. The PRAYOG BOARD is based on Intel strong Arm microprocessor (SA1110). For checking the efficiency of that ARM platform, different programs are required. Different type of communication (Unicast/Multicast/Broadcast) programs in Linux is implemented on this ARM platform. The operating system used in PRAYOG BOARD is LINUX. The Language used to write a software program is C. Using this language we can simulate this project also.
Implant training Details :

Industry : KELTRON Component Complex Ltd., Kannur
Duration : 24 May 2005-07 June 2005
Products : Aluminum electrolytic DC&AC Capacitor & resistor
Description
The company started with manufacture of axial, radial and can type Dc capacitors. Subsequently products were added with in-house development .At present the company manufactures a wide range of Aluminum Electrolytic Dc & AC Capacitors. The capacitor elements are impregnated in electrolyte used in production of Aluminum Electrolytic capacitor.
Area of Interest:
- VLSI Design
- Microelectronics
- Digital Design
Hobbies
Listening Music, Net Surfing, Watching Films& Reading Magazines.
Imperative efficiency
Creative, self motivated to learn anything and everything.
Strength:
- Working in a Team.
- Eagerness to Explore and Learn.
Declaration
I hereby declare that the above given information’s are true and correct to the best of my knowledge and belief. Reference could be provided on request
Place: Chunda
Date: (ADARSH KS)
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More Information about this submission and submitter:-
___________________________________________________
Submission ID : 4254291
Date & Time : 15th Jun 2011 4:11 AM (UTC)
IP Address : 122.179.42.13
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