Electronics Communication Engineer ECE : Resume CV

[bhupe0026]

Resume :
Bhupendra Singh
Email : bhupe0026 AT gmail.com, bhupendra_singh0026 AT yahoo.co.in

Objective :
To work in a progressive organization where my education, capabilities, creative ideas, professional and personnel skills are best utilized along with the goals of the organization.

Educational Details :
Professional Qualification :
B. Tech. : (Electronics and Communication)
College : Sagar Institute of Technology & Management , Barabanki(UPTU).
Aggregate percentage : 67.8%

Technical Qualification :
- Operating System : Windows 98/ 2003, Windows XP.
- Package : Microsoft Office 2003 &2007.
- Language : C, C++, Java.

Academic Qualification :
CLASS SCHOOL/COLLEGE PERCENTAGE :
HIGH SCHOOL CITY MONTESSORI SCHOOL, ALIGANJ,LUCKNOW 78%
INTERMEDIATE ST.FIDELIS COLLEGE, LUCKNOW 80%

Trainings :
(i) Summer/Project Training on Operating & Working Environment of Various Divisions (GSM Technologies) from 1ST July to 30th July, 2009 at ITI Limited, Mankapur.
(ii) HINDUSTAN AERONOTICAL LIMITED from 15th June to 15th July 2008.
(iii) Training on Internet ship on Jsp, Servelet Struts from SoftPro India from 8TH July to 8th August.
(iv) Training on BSS AND RADIO NETWORKS from COGNITEL TRAINING PRIVATE LTD
Project Undertaken :
- Gas Leakage Detection And Auto Off
Key Skills :
Good communication skill,Hard Working, Team Player, Patience, Leadership skills.

Co-curricular Activities :
1. Participated in excellence 2009 and 2010 as coordinator in model presentation and other cultural events.
2. Participated in excellence (college fest ) in 2008 in model presentation and was declared winner and also in other technical as well as cultural programme.

Hobbies :
Internet surfing ,listening to songs & playing cricket.

Personal Details :
Date of Birth : 26/12/1988
Marital Status : Single

BHUPENDRA SINGH

[Guest-IJT]

RESUME :
THIRUMAL.M
E-mail : th71comniq AT gmail.com

OBJECTIVE :
To Gain recognition as a Pro-Active, Innovative and Versatile Hardware
Professional.

CAREER SUMMARY :
- Bachelor of Engineering in Electronics and Communication.
- Handled projects in Digital designs such as Multiprocessors in FPGA,
Text Hiding in Audio signal, 16-QAM (SDR) Simulink Model in FPGA,
FHSS, DSSS and Encryption algorithms like E0 Cipher, SEA, and CSA.

WORK EXPERIENCE :
- Working as “RTL DESIGN ENGINEER” in Femto Logic Design Pvt Ltd.Chennai from August 2009 to till date.
- Interfaced ALTERA FPGA Boards - DE0, DE1, DE2,
XILINX FPGA Boards – SPARTAN3E, VIRTEX-5.

EDUCATIONAL QUALIFICATION :
Degree / Qualification Name of the Institute / School Mark Scored Academic Year :
BACHELOROF ENGINEERING(ECE) ARULMIGU MEENAKSHI AMMAN COLLEGE OF ENGINEERING (Affiliated to Anna University) 75% 2005– 2009
Higher Secondary Course Certificate UNITY MATRICULATION HIGHER SECONDARY SCHOOL DHARMAPURI 90.41% 2003-2005
Secondary School Leaving Certificate GOVT HIGHER SECONDARY SCHOOL DHARMAPURI 90.2% 2001-2003

PERSONAL SKILLS :
- Optimist.
- Possess Leadership qualities.
- Ability to think practically.
- Presentation skill.
- Potential to manage stress and Time.

SOFTWARE PROFICIENY :
- Operating Systems
- Windows XP/7.
- Basics of LINUX.
- Languages
- VERILOG.
- VHDL
- C & C++
- EDA tools
- ALTERA Quartus II
- Xilinx ISE.
- Modelsim 6.4a
- Integrated Software Tools.
- NIOS II IDE.
- SOPC Tool.
- MATLAB-SIMULINK.

AREA OF INTEREST :
- Digital Design.
- VLSI.
- Electronic Devices.
- Communication & Signal Processing fields.

AWARDS AND HONORS RECEIVED :
- Certified student from IIT-MADRAS (ANALOG DEVICES-DSP Learning Centre).
- Rank holder in 12th, 10th and Good in taking Seminars.
- Won Fourth Place in National Level Technical Symposium Organized by SCSVMV University.
- Did my INPLANT TRANING IN BSNL.

PROJECTS HANDLED :
Implementation of Multiprocessor in FPGA :
Description :
For many applications, allocating performance among all of the tasks in a System-On-Chip (SOC) design is much easier with multiple CPUs than with just one control processor and multiple blocks of logic. Multiple processor design changes the role of processors, allowing programmability to be designed into many functions while keeping power budgets & Memory Blocks under control.
TEAM SIZE : 3 members.
RESPONSIBILITIES :
- Build system for Multiprocessor in SoPC.
- Synchronized all the modules into top module.
- Implementation of Multiple Applications in ALTERA DE boards.

Implementation of Text Hiding in Audio signal in FPGA :
Description :
Audio Steganography is one of the most effective ways to protect our privacy. The main goal of audio Steganography is to hide messages inside the audio in a way that does not allow any enemy to even detect that there is a second secret text message present in the audio. The original data is encrypted by using a key. Then the encrypted data is hidden in an audio file. To recover the original data the encoded audio file is decoded and then it is decrypted. In all the above process the quality of the audio file kept undisturbed.
TEAM SIZE : 3 members.
RESPONSIBILITIES :
- Written Verilog code for Encryption.
- Written Implementation coding for LCD Interface.
- Interface Audio signals with ALTERA Boards

Cryptanalysis of Bluetooth Encryption :
Description :
Bluetooth offers methods for generating keys, authenticating users, and encrypting data. The data encryption mechanism of the Bluetooth standard is a stream cipher that is generated by an LFSR based key stream generator, E0, and XOR ed with the plaintext. Our method requires 128 known bits of the key stream in order to recover the initial state of the LFSRs, which reflects the secret key of this encryption engine.
TEAM SIZE : 2 members.
RESPONSIBILITIES :
- Designed LFSR Blocks block in VERILOG.
- Optimization of Power & Timing constraints through Quartus-II.
- Implementation coding for LCD & Key Board Interface.
16-QAM (SOFTWARE DEFINED RADIO) Simulink Model in FPGA
Description :
Software defined radio (SDR) has emerged as a priority theme of research since it will substitute for conventional implementation on wireless communication system. In this paper, a multi-standards SDR model is designed and implemented in FPGA form using Xilinx system generator technique.
According to the under sampling theory which is used in this model, and its performance of the proposed model with different standards’ like GSM,OFDM, and WCDMA using 16QAM modem is produced attractive behavior with different channel effective and minimum BER. Therefore the effectiveness leads to transition from 3G to 4G of wireless systems.
TEAM SIZE : 4 members.
RESPONSIBILITIES:
- Designed Transmitter Block & Filter designs in Simulink.
- Generate Hdl code using System generator and implemented
In Virtex-5 Board.
FPGA IMPLEMENTATION OF FHSS:
Description:
In this project the message to be transmitted is digitized and mixed with a Pseudo-Random sequence which is many times the rate of the information signal. This results in spreading the signal over a wider bandwidth. Each word thus generated is assigned a particular frequency (within the available bandwidth) and then it is transmitted.
The signal thus transmitted bears no resemblance to the original message and so it can't be received by any "random" receiver only the receiver having the same PN sequence can decode the message. Then the whole system is implemented in SPARTAN FPGA by using the XILINX ISE.
TEAM SIZE : 3 members.
RESPONSIBILITIES:
- Designed Transmitter Block in VHDL
- Program for Samples generation in C.
- Verification of ROM blocks in Receiver.

PERSONAL DETAILS :
Date of Birth : MAY 11, 1988
Gender : Male
Languages known : English, Tamil.
Nationality : Indian

DECLARATION :
All the information furnished above is true to the best of my knowledge. I am willing to produce necessary original certificates on demand.

PLACE : Chennai
DATE :13.11.2010
(THIRUMAL.M)

[amaanjmi]

RESPECTED SIR,
I HAVE ENCLOSED MY UPDATED CV, PLZ CONSIDER WITH ME.

THANKS
JAMAL AMIN