www.sandeepani-vlsi.com School of VLSI Design Bangalore : FPGA, EDA, Embedded, ASIC, ,Verilog Professional Course

[mskavi]

Sandeepani School of VLSI Design Bengaluru/Bangalore : Professional Development Course on Designing VLSI /Embedded SOC
Website: http://www.sandeepani-vlsi.com

Keywords: FPGA, EDA, VLSI, Embedded, ASIC,board design,Verilog, VHDL,DSP, Xilinx, ARM,RTOS,MicroC,Embedded Linux,SOC,

Designation: Professional Development Course on Designing VLSI /Embedded SOC
Experience: 0 - 2 Years
Location: Bengaluru/Bangalore
Education:
UG - B.Tech/B.E. - Computers, Electrical, Electronics/Telecomunication, Instrumentation
PG - M.Tech - Any Specialization, Computers, Electrical, Electronics/Telecomunication, Instrumentation
Industry Type: Semiconductors/ Electronics
Functional Area: Embedded/EDA /VLSI/ASIC/Chip Design
Posted Date: 02 Jun 2009

Job Description:

Are you worried about slowdown and not able to decide what to do? It is the right time to enhance your skills in line with your area of interest & background. So don’t wait till the market improves, under go industry oriented & certified training, which will add value to your resume as well as gives real time project experience & hands on exposure. This will increase your employability even in the slowdown as companies search for industry ready engineers to save cost on training after recruitment. Sandeepani (A Division of CoreEL Technologies (I) Pvt. Ltd. a decade old Semiconductor Company – www.coreel.com) offers customized career specific Professional Development Course for fresh engineering graduates from Electrical / Electronics and Communication, Telecommunication, Instrumentation and Computer Science Engineering Disciplines in VLSI Design Designing Embedded System-On-Chip These programs are specifically designed with an objective to create quality manpower in the fields of VLSI Design, VLSI System Design with FPGAS and Embedded System Design engineering, imparting quality hands-on training from ‘concept-to-project’, covering design methodology using industry standard tools and practices. Training is delivered by in house industry experts with design experience of 5 to 20 years in semiconductor industry.

Desired Candidate Profile:

BE / ME in EE, E&C, CSE, IT, Telecom or Instrumentation with minimum 60% Aggregate

Company Profile:
Sandeepani - School of VLSI Design is an institution of higher learning with a mission that incorporates teaching, research, creative activity and service.

The Sandeepani is recognized as a specialized VLSI / Embedded training school both by India's fast growing VLSI / Embedded professionals and the new engineering graduates planning to enter this design field.

Sandeepani has state-of-the-art facilities for high-end VLSI, Programmable Logic system design and Embedded system training. Facilities include modular classrooms, fully networked and web-enabled, Linux workstations for every student apart from high end Windows based systems. It is also equipped with complete suite of EDA tools from Xilinx

Sandeepani is an Authorized Training Center in association with Mentor Graphics Inc, USA and Xilinx.

Executive Name: Manjula /Harish

Address:
CoreEl Technologies
#21, 7th Main, I Block,
Koramangala
Bangalore,Karnataka,INDIA 560034

Email Address: harish@sandeepani-vlsi.com

Telephone: 91-80-41970441

Reference ID:
Sandeepani

Keywords: FPGA, EDA, VLSI, Embedded, ASIC,board design,Verilog, VHDL,DSP, Xilinx, ARM,RTOS,MicroC,Embedded Linux,SOC,

[nandabp]

Hi Harish,

I am B.P.Nanda completed my BE in Electronics & Communication in the year 2010 from East Point College of Engineering and Technology, Bangalore; Visvesvaraya Technological University, Belgaum with an aggregate of 64.05%.

I have Worked on IEEE papers on VLSI for my final year project.

Please find Attachments for my resume.

PROJECT DETAILS:

Implementation of 2D-DA DWT/IDWT architecture on FPGA for image compression.

Ø Image compression is an integral part of any image processing unit. Compression of image is based on JPEG 2000 standards. JPEG 2000 recommends use of wavelets and encoding schemes for compression.

Ø DWT is the most time consuming unit and is also very intensive mathematics, and consumes large power due to large number of arithmetic operations. Multipliers and adders are the major arithmetic units of a DWT processor.

Ø Implementation of DWT on Field Programmable Gate Arrays is one of the most challenging activities that are addressed by many of the research activities.

Ø As the hardware resources on FPGA are limited, it is required to optimize the DWT architecture, so that it consumes limited number of slices and also operates at very high frequency.

Ø In this current project, Distributive Arithmetic (DA) based DWT architecture is modified.

Ø The DA architecture is modified by splitting the existing LUT’s into two parts, and splitting the inputs into even and odd terms. This introduces parallelism in the DA architecture and hence the speed is increased.

Ø Mat lab reference model is developed and validated with different images. HDL models are developed for the modified DA architecture and are implemented on FPGA.

Ø DWT architecture implemented on FPGA is verified by interfacing memory and VGA controller for input and output display.

Ø The modified DA results are compared with basic DWT results with respect to speed and area.

Team size : 4

Tools : Xilinx ISE 10.1 and 7.1i

Hardware Description Language: Verilog

Simulators : Modelsim simulator 5.7g

Responsibilities : Designing the architecture, Developed codes, RTL design, FPGA Implementation, performed optimization in terms of area, Power and time.

Reference : IEEE papers.

Thank you,
Nanda.B.P

[Guest]

Kishore.B.R
Email ID : kishore.ramesh AT gmail.com


CAREER OBJECTIVE
- To work in a challenging environment, enrich my skills and grow myself as an excellent team player and a technical lead who can influence the team and help the company grow as one among the best in the industry.
PROFESSIONAL QUALIFICATION

Qualification


Institution

University
Year of passing
Percentage
of marks
(%)

B.E. (Electronics&
communication
Engg.)
THE OXFORD COLLEGE OF ENGG
Visvesvaraya
Technological
University,
Belgaum
2010

60
EDUCATIONAL QUALIFICATION
Qualification Institution Board
Year of passing
Percentage
of marks
(%)

S.S.L.C
St,anne’s High School Mulbagal, Kolar KSEEB
2003
71.84%.
DIPLOMA Government Polytechnic, Chintamani DIRECTORATE OF TECHNICAL EDUCATION
2006 69.33%
STRENGTH
- Hardworking
- Ability to move within a team and share my ideas and visions.
AREAS OF INTEREST
- DIGITAL ELECTRONICS
- COMMUNICATION

TECHNICAL SKILLS
- Microprocessor 8086, Microcontroller 8051.
- Comfortable with windows environment.
FINAL YEAR PROJECT

PROJECT TITLE : FACE RECOGNITION AUTHENTICATION AND SECURITY SYSTEM
Duration : 4 months (FEB 10-MAY 10).
Description : Using face as password for opening door.

WORK EXPERIENCE
7 months experience as Project Engineer for DRDO sponsored project “Study on propagation of RF / Microwave signal in SAND/DUST and PLASMA media” in M.S. Ramaiah Institute of Technology Bangalore, from 25th October 2010.
One year experience as Lab Assistant in Sri Venkateshwara College of Engg, From 2006 – 2007, immediately after completing my Diploma.