South East Central Railway RRC Recruitment 2011 www.secr.indianrailways.gov.in : Cultural Quota

[muthukalee]

Name of the organisation : SOUTH EAST CENTRAL RAILWAY ( SECR)
Name of the post : Railway Recruitment Cell(RRC) Recruitment for Cultural Quota in 2011

SOUTH EAST CENTRAL RAILWAY
RAILWAY RECRUITMENT CELL

RECRUITMENT AGAINST CULTURAL QUOTA

Applications are invited in the prescribed format from eligible candidates for recruitment to 2 (Two) posts in Group ‘C’ categories against cultural quota to be recruited in Pay Band-1 Rs.5200-20200 on Grade Pay Rs.1900/-/Pay Band-1 Rs.5200-20200 on Grade Pay Rs.2000/- on South East Central Railway in the following disciplines for the year 2011-12:-

DETAILS OF POSTS/DISCIPLINES :

Discipline : Classical Dance (Odissi/Bharatnatyam)
No. of post : 01
Essential qualification : Possession of Degree/Diploma/Certificate in relevant Classical Dance (Odissi/Bharatnatyam) disciplines from government/ any government recognized institutes.

Discipline : String Instrumental
No. of post : 01
Essential qualification : Possession of Degree/Diploma/Certificate in relevant String Instrumental disciplines from government/ any government recognized institutes.

ACADEMIC QUALIFICATIONS :
FOR POSTS - NON-TECHNICAL POPULAR CATEGORIES
Passed Matriculation or its equivalent with not less than 50%marks in aggregate. Minimum percentage of 50% marks in aggregate is not applicable to SC/ST candidates and to those candidates (Irrespective of community),who possess qualifications higher than matriculation such as HSC/Intermediate/Graduation/Post Graduation.(or)
FOR POSTS - TECHNICAL CATEGORIES
Act Apprenticeship / ITI . No other qualification including Diploma in Engineering will be accepted as an alternative.
Act Apprenticeship / ITI Certificate must be approved by SCVT/NCVT.

AGE LIMITS : Candidates should have attained age of 18 years and should not have completed 30 years as on 01.01.2012.The upper age relax-able by 03 years for candidates belonging to OBC communities, by 05 years for candidates belonging to SC/ST communities.

SCALE OF PAY :- PB-1 Rs. 5200-20200 + Grade Pay Rs. 1900/- (RSRP)/ PB-1 Rs. 5200-20200 + Grade Pay Rs. 2000/- (RSRP)

WHOM TO APPLY :-
Application should be addressed to and sent by post to the
Dy Chief Personnel Officer(Recruitment),
Railway Recruitment Cell(RRC),
South East Central Railway,
R.T.S. Colony, Bilaspur (Chhattisgarh)- 495004

Application received after 18.00 hrs of 26.09.2011 shall not be entertained.

More Details : http://www.secr.indianrailways.gov.i...l%20quota..doc

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General Instructions :
This is information on SOUTH EAST CENTRAL RAILWAY ( SECR) Recruitment 2011 / Vacancies / Careers / to be filled, for the post of Railway Recruitment Cell(RRC) Cultural Quota .
If you are looking for jobs / career in SOUTH EAST CENTRAL RAILWAY ( SECR), you have to apply by downloading the application form given in the link above.
Full details of recruitment in SOUTH EAST CENTRAL RAILWAY ( SECR) can be had from the detailed advertisement link as given above.
You can also visit the careers page of SOUTH EAST CENTRAL RAILWAY ( SECR) to know more about the selection procedure, latest results, other jobs vacancy requirements etc.
Please ensure that you apply before the last date as all government recruitment procedures adhere a strict policy on this.
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[Guest-IJT]

Name : sivaprasad
Email : siva2088 AT gmail.com
Designation / Skillset : msc vlsidesign
sivaprasad godugunuri

Resume :

Career Objective :
Seeking an opportunity to work in a challenging environment and utilize my knowledge and skills in the field of VLSI circuit design, CMOS device digital design and verification.
Summary of Qualifications :
- Good understanding of the ASIC and FPGA design flow
- Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog
- Very good knowledge in verification methodologies
- Experience in using industry standard EDA tools for the front-end design and verification
VLSI Domain Skills :
HDLs : Verilog and VHDL
HVL : SystemVerilog
EDA Tool : Modelsim and ISE
Domain : ASIC/FPGA Design Flow, Digital Design methodologies
Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis,
Software Skills :
Languages : C
Operating System : Windows, Linux
Professional Qualification :
Maven Silicon Certified Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Center, Bangalore Year : Feb 2011
Academic exposure :
Course University/Institute Year Percentage
M.Sc (Tech) VLSI Design Andhra University, Vizag,
Andhra Pradesh 2011 8.53/10 CGPA
B.Sc (Maths,Physics,Electronics&Electrical Technology) PNC&KR Degree College,Narasaraopet
Nagarjuna University, Guntur 2008 78.6
Intermediate(MPC) Andhra Pradesh State Intermediate Board
Sri Vikas JuniorCollege,
Dachepalli, Guntur 2005 73.4
SSC(10th) Andhra Pradesh State Secondary Education Board, ZPHS,V.Reddypalem,Guntur 2003 74
Certifications :
Attended many National seminars on VLSI & Embedded Systems in Andhra University.
Passport details :
Passport number : J5117956
Issued date :29-03-2011
Issued place : Visakhapatnam
ACADEMIC PROJECT :
An FPGA Implementation of 30Gbps Security Module for GPON Systems
Organization : AU CAMPUS (Academic Project in 6th Semester)
Team Size : 2
HDL : VHDL
EDA Tools : Modelsim, Questa – Verification Platform and ISE
- GPON systems require gigabit throughput data encryption for security and privacy. This paper presents an implementation of very high speed security module for GPON on Virtex4 FPGA. The security module supports payload encryption with constant delay by using counter mode AES algorithm. Our design of AES has three advanced features: composite field arithmetic Sub Byte, efficient Mix Column transformation, and On-the-Fly Key-Scheduling. Full-pipelined architecture is employed for the AES architecture in order to achieve the high performance for security module. The experiment shows that the proposed architecture can achieve a throughput of 30Gbits/s on a Xilinx Virtex-4 VLX100-12 device. The performance of our design is well suitable for encryption applications of GPON systems
VLSI Projects in MAVAN SILICON:
Real Time Clock – RTL design and verification
Organization : MAVEN SILICON
Team Size : 2
Duration : 15 days
HDL : Verilog
HVL : SystemVerilog
EDA Tools : Modelsim, Questa – Verification Platform and ISE
- Implemented the Real Time Clock using Verilog HDL independently
- Architected the class based verification environment using SystemVerilog
- Verified the RTL model using SystemVerilog.
- Generated functional and code coverage for the RTL verification sign-off
- Synthesized the design
Dual Port RAM – verification
Organization : MAVEN SILICON
Team Size : 2
Duration : 1 week
HDL : Verilog
HVL : System Verilog
EDA Tools : Modelsim, Questa – Verification Platform and ISE
- Implemented the Dual Port Ram using Verilog HDL independently
- Architected the class based verification environment using system Verilog
- Verified the RTL module using System Verilog
- Generated functional and code coverage for the RTL verification sign-off
Video Graphics Adaptor – RTL Design and Verification
Organization : MAVEN SILICON
Team Size : 2
Duration : 1 month
HDL : Verilog
EDA Tools : Modelsim, Questa – Verification Platform and ISE
- Architected the design
- Implemented the RTL using Verilog HDL
- Verified the RTL using Verilog HDL
- Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board

DECLARATION:
I, G.SIVAPRASAD do here by confirm that all the above mentioned information is true and to the best of my knowledge.
Place:
Date:
Sivaprasad.G
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More Information about this submission and submitter:-
___________________________________________________
Submission ID : 4452197
Date & Time : 6th Aug 2011 12:32 PM (UTC)
IP Address : 117.242.248.103
Browser Info : Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.20) Gecko/20081217 BTRS7181 Firefox/2.0.0.20
Predicted Country : India

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