Ask Question / Post resume

Post a reply to the thread: www.trivenigroup.com Triveni Engineering & Industries Ltd Noida : Site In charge

Your Message

Your Username:

Notes:-
1) You can copy and paste your full resume in the box below.
2) Or you can ask your question. We try to answer, as far as possible.

Title:

[QUOTE=Unregistered;289861]RESUME
[b][u][b][u]Y.SATYADEV[/u][/b] [/u][/b]: 
[b][u][b][u]EMAIL [/u][/b] [/u][/b]: satyadev4c0 AT gmail.com

[b][u][b][u]OBJECTIVE [/u][/b] [/u][/b]:
Seeking an opportunity to be a part of a reputed organization where I can utilize my personal skills in a challenging and innovative environment that helps me to achieve my personal and organizational goals.

[b][u][b][u]EDUCATIONAL QUALIFICATIONS [/u][/b] [/u][/b]:
Year of Studying Course of study Stream Institution University/ Board Percentage 2010 NOV-2013 JAN M.Tech
 DECS Gudlavalleru Engineering College, Gudlavalleru. JNTUK 69.00 2006-2010 
B.Tech ECE Rao & Naidu Engineering College, Ongole. JNTUK 61.97 2004-2006 
Intermediate MPC Nalanda Junior College of science & arts, nGuntur. Board of Intermediate Education 78.90 2003-2004 
S.S.C S.M.R.M. High School, Nagaram. Board of Secondary Education 76.50

[b][u][b][u]ACHIEVEMENTS [/u][/b] [/u][/b]:
1. I published a paper “An Efficient Reversible Design of BCD Adder” in International Journal.
 
[b][u][b][u]TECHNICAL SKILLS [/u][/b] [/u][/b]:
[b][u][b][u]Interested subjects [/u][/b] [/u][/b]: Digital signal processing, Digital communication, Analog
 Communication, Electronics devices and circuits.
[b][u][b][u]Languages [/u][/b] [/u][/b]: MS -OFFICE, C.

[b][u][b][u]PROJECT DETAILS [/u][/b] [/u][/b]:
[b][u][b][u]M-TECH PROJECT [/u][/b] [/u][/b]: An Efficient Reversible Design of BCD Adder.
Design of area- and power-efficient high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In the hardware design, binary computing is preferred over decimal computing because of ease in building hardware based on binary number system. The design of high-speed and low-power VLSI architectures needs efficient arithmetic processing units, which are optimized for the performance parameters, namely, speed and power consumption. Adders are the key components in general purpose microprocessors and digital signal processors. They also find use in many other functions such as subtraction, multiplication and division.
This project proposes design of the reversible BCD adder using reversible gates. The reversible gates used in this project are the NOT gate, the CNOT gate, the Toffoli gate and the Peres gate. This project can be analyzed the performance of the reversible design of BCD adder. In this project power consumption, delay and area of reversible BCD adder can be calculated

[b][u][b][u]B-TECH PROJECT [/u][/b] [/u][/b]: Hiding the Information Using Mat-Lab Programming.
Steganography & cryptography is the practice of hiding private or sensitive information within something that appears to be nothing out of the usual. Steganography is often confused with cryptology because the two are similar in the way that both are used to protect important information.
The difference between the two is that Steganography involves hiding information so it appears that no information is hidden at all. If a person or persons views the object that the information is hidden inside of he or she will have no idea that there is any hidden information, therefore the person will not attempt to decrypt the information.

[b][u][b][u]PERSONAL PROFILE [/u][/b] [/u][/b]:
[b][u][b][u]Name [/u][/b] [/u][/b]: Y.SATYADEV
[b][u][b][u]Father’s Name [/u][/b] [/u][/b]: Y.Visweswararao
[b][u][b][u]Date of Birth [/u][/b] [/u][/b]: 25-Jun-1989
[b][u][b][u]Languages Known [/u][/b] [/u][/b]: English, Telugu
[b][u][b][u]Sex [/u][/b] [/u][/b]: Male
[b][u][b][u]Marital status [/u][/b] [/u][/b]: Unmarried
[b][u][b][u]E-Mail [/u][/b] [/u][/b]: satyadev4c0 AT gmail.com
[b][u][b][u]Strengths [/u][/b] [/u][/b]: Smart working, Positive attitude, Effective communication.

[b][u][b][u]Declaration [/u][/b] [/u][/b]: 
I hereby declare that all the details given above are true to the best of my knowledge and belief.

[b][u][b][u]Date [/u][/b] [/u][/b]:
 (Y.Satyadev)
[b][u][b][u]Place [/u][/b] [/u][/b]:[/QUOTE]

All times are GMT +5.5. The time now is 12:06 PM.