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www.sanved-da.com Bangalore : FPGA Design Engineer
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[QUOTE=ijt.viji;208229][B]Company Name [/B]: Sanved DA(sanved-da.com) [B]Company Location [/B]: Bangalore [B]Designation [/B]: FPGA Design Engineer [URL]http://www.sanved-da.com/careers.php?page=Careers[/URL] [B]Careers [/B]: [B]1)Designation [/B]: Design Engineer [B]Education Qualification [/B]: BSEE / MSEE [B]Experience in years [/B]: 3 - 8 yrs [B]Location [/B]: Bangalore [B]Job Code [/B]: Front - end Design [B]Category [/B]: semiconductor Jobs [B]Description [/B]: Experience with standard cell ASIC and / FPGA design Expert in RTL Coding (Verilog / VHDL) Gate level design and verification Knowledge of all phases of ASIC design methodology Module Level Designs - Micro Architecture, Design, Verification SoC Integration Timing Analysis Linux/Unix environment Effective Communication skills and a Team Player [B]Desired Capabilities [/B]: Knowledge of Bus Protocols like AMBA, AXI, AHB, SPI, USB, and Ethernet Protocol Familiar with ARM microprocessors Working Knowledge of System Verilog FPGA based designs Code Quality and Equivalence [B]2)Designation [/B]: Design Verification Engineer [B]Education Qualification [/B]: BSEE / MSEE [B]Experience in years [/B]: 2 - 8yrs [B]Location [/B]: Bangalore [B]Job Code [/B]: Design Verification [B]Category [/B]: Semiconductor Jobs [B]Description [/B]: SOC verification done on at least one project with constrained random methodology (eRM/VMM/OVM) Proficiency in System Verilog / Specman / C++ / Vera / e / System C / test builder. Strong domain knowledge on PCIe / USB / Ethernet / ARM / AHB/ AXI / AMBA Build verification environment with any of the above methodology Writing and debugging test cases. Code coverage and functional coverage. Expertise in Verilog / VHDL is desired Working knowledge of scripting language like Perl / Python / Unix Make/ Unix Shell Scripts [B]3)Designation [/B]: Physical Design Engineer [B]Education Qualification [/B]: BSEE / MSEE [B]Experience in years [/B]: 2 - 10yrs [B]Location [/B]: Bangalore [B]Job Code [/B]: Physical Design [B]Category [/B]: Semiconductor Jobs [B]Description [/B]: Understanding Deep Sub micron effects such as 90nm and below Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm & 65nm) Understanding OCV, DFM, DFY [B]4)Designation [/B]: Design Engineer [B]Education Qualification [/B]: BSEE / MSEE [B]Experience in years [/B]: 3 - 8 yrs [B]Location [/B]: Bangalore [B]Job Code [/B]: Synthesis / STA [B]Category [/B]:Semiconductor Jobs [B]Description [/B]: Experience in leading chip level synthesis/STA Worked on 45nm technology Expertise in Synthesis, STA, Timing Constraints, Timing Closure Hands on experience of working with RTL Compiler and Gold Time Working experience in TCL is a plus Knowledge of Networking domain is an added advantage Working knowledge of DDR is an added advantage [B]send your resume [/B]: [EMAIL="contact@sanved-da.com"]contact@sanved-da.com[/EMAIL] [B]Contact us [/B]: Sanved DA #3623,13th G Man , 7th cross , Half 2nd stage Indiranagar , Bangalore - 560 008, India.[/QUOTE]
