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[QUOTE=Guest;165273]Doddigarla Vijay Kumar 
 [b]email-id [/b]: vijaykumar.doddigarla AT gmail.com 
CAREER OBJECTIVE
To be associated with a Progressive and Innovative Organization that gives scope to apply my knowledge and skills and to be a part of a team that dynamically works towards the growth of the Organization.
QUALIFICATIONS
- Good in programming in C, Java.
- Excellent organizational and problem solving skills, Hardworking, zeal to learn and interact, commitment.
- Knowledge of Microsoft Word, Excel, and PowerPoint.
[b]EDUCATIONAL PERFORMANCE  [/b]: 
Education Period From To School/College Board/University Percentage
B.Tech. (E.C.E.) 2007 2011 Vignana Bharathi Institute of Technology J.N.T.U 57.5%
Intermediate 2004 2007 Vijayawada nalanda junior college Board of Intermediate Education 54%
S.S.C. 2003 2004 Sree Vani High School Patancheru Board of Secondary Education 77%
PROJECT
[b]Title [/b]: GSM BASED DC MOTOR BIDIRECTIONAL CONTROL 
[b]Design Goal [/b]: The goal of the project is to develop a system, which uses Mobile technology to control DC Bi Directionally, which executes with respect to the signal sent by the mobile.
[b]Implementation [/b]: 
 For utilization of appliances the new concept has been thought to manage them remotely by using GSM, which enables the user to remotely control switching of domestic appliances. Just by dialing keypad of remote telephone, from where you are calling you can perform ON / OFF operation of the appliances. 
[b]Title [/b]: DESUGN AND IMPLEMENTATION OF 32-BIT RISC PROCESSOR
[b]Design Goal [/b]: The RISC (Reduced Instruction Set Computer) must use simple constructs and have small instruction set. It is basically designed in order to achieve faster executions. The striking feature of RISC is that, it executes each instruction within one clock cycle. This is achieved carrying out most of the operation with in the Processor and minimizing the use of frequent operations requiring slower peripherals. An important aspect of the instruction set is that it is easy to decode (Fixed length instruction format). Thus the Opcode and Instruction Register fields can be accessed simultaneously
IMPLEMENTARION: This RISC processor is designed to incorporate 20 basic instructions involving Arithmetic, Logical, Data Transfer and Control instructions. The Instruction format contains first four MSB bits as OPCODE and remaining 28bits as Address bus. It can address 256Gbytes of memory locations and 32-bit Bi-directional Data Bus. The Processors includes instructions like Arithmetic, Logical, Control, Data transfer, Register Transfer and Some of the functional blocks of RISC processor design includes: Program Counter, Instruction Register, Arithmetic Logic Unit (ALU), Register organization, Control & Decoding Unit, Memory block, Data path design and glue logic.[/QUOTE]

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