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Title:

[QUOTE=Guest;124571]D.Sathishkumar
 
[b]Career Objective [/b]:
Young graduate, Multi talented, Resourceful and knowledgeable, to work in a dynamic environment that offers me a consistently positive atmosphere to learn new technologies and implement them for the betterment of the concern.
[b]Skills [/b]:
- Good Communication Skill 
- Good Listener
- Team facilitator
[b]Academics [/b]:
[b]- Bachelor Degree  [/b]: BE (Electronics and Communication),72%,
 Paavai College of Engineering.
[b]- University  [/b]: Anna University, Tamilnadu, India
[b]Academics Projects [/b]:
Mini Project
[b]Project title [/b]: Sms based home appliances 
[b]Role [/b]: 
- Involved in operating the home appliances like television, washing machine etc. 
- It has been carried out through sensors by short messaging services. 
[b]Environment [/b]: pic microcontroller Processors, sensor 
[b]Description [/b]: The system involved in designing of sensor which controls the operation of various home appliances trough short messaging service. For example during hot weather we can switch on our air conditioner by sending an SMS.
 
[b]Final year project  [/b]: 
 [b]Project title [/b]: VLSI Design of 2-D DWT for area efficient and high-speed image compression.
[b]Role [/b]:
- Involved in designing of parallel architecture for high speed and real-time 2-D Discrete Wavelet Transform using SRAM and FIFO memory. 
- Developed a architecture based on new and fast convolution approach, reduces the hardware complexity in addition to reduce the critical path to the multiplier delay. 
- Designed with an efficient memory area to produce one output in every cycle. 
- The system has been verified, using JPEG2000 coefficients filters on XILINX Virtex-II Field Programmable Gate Array. 
- Produced high-speed processing as well as high PSNR quality. 
[b]Environment [/b]: 2-D DWT, JPEG2000, FPGA, Encoders, Compression Techniques. 
[b]Description [/b]: The system Involved in designing of high speed and real-time 2-D Discrete Wavelet Transform and starts the column-processing as soon as sufficient numbers of rows have been filtered. Two fast convolution based blocks, for the two dimensional (2-D) discrete wavelet transform (DWT), are used to accelerate the computing
The Xilinx Virtex-II FPGA implementation ,of developed architecture using the (9,7) filter , required eight FIFO memory in dual-Port-Mode.
The (3,5) 2-D wavelet filter uses only 8kb of memory with 256*256 image size and the (9,7) one uses only 16 kb.
[b]Certificates  [/b]:
- “ADVANCED COMMUNICATION SERVICE ACHITEECTURE USING WIRELESS MEFH NETWORK” in SRM.
- “A SECURED CROSS LAYER MULTIPATH ROUTING FOR MD VIDEO IN WORELESS MEFH NETWORK” in Vivekananda college of engineering.
- “IMAGE COMRESSION PROCESS BY DIRECTION ADAPTIVE DISCRETE WAVELET TRANSFORM(DADWT) TECHNIQE” in pavendar bharathidasan college of engineering. 
- I had participated in circuit debugging in National level technical symposiums.
- I had participated in PCB design workshop in national level technical symposium.
- I have secured many positions in college level athletics. 
[b]- Computer Exposure [/b]:
 
- Basic C Programming
- Computer Networks
[b]Work Experience [/b]:
[b]September 2010 to Till date  [/b]: Integrated wireless solutions Pvt Ltd 
 
[b]Position held  [/b]: RF Engineer
[b]Responsibilities [/b]:
- Receiving Inputs from the Customer.
- Plotting inputs in Map Info.
- Analyzing type of survey to be done (Capacity or Coverage)
- Doing survey according to the requirement.
- Selecting the candidates according to the requirements both for RND & TND.
- Frequent coordination with coordinator for proper output.
- Analyzing the candidates.
- Creating Reports and delivering at committed time. 
- Doing Survey like Capacity, Coverage and separate TND Survey for RSL achievement as per customers requirement.
- Doing Drive test on 2G & 3G for analyzing Rx level, quality and other parameters and optimization[/QUOTE]

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