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[QUOTE=Guest-IJT;109825][b]Name [/b]: vinjamuri sricharan [b]Email [/b]: sricharan4a8 AT yahoo.co.in [b]Designation / Skillset[/b] : software tester [u][b]Resume[/b][/u] : Career Objective To achieve good technical and management skills and utilize them to contribute to the growth of the organization and to touch the pinnacles of success.. Technical Exposure [b]Operating System [/b]: Windows 2000, XP, MS- DOS [b]Languages [/b]: VHDL / VERILOG [b]Software Exposure [/b]: XILINX ISE, MICROWIND, PSPICE Software testing SDLC, STLC, Regression Testing, Integration Testing, System Testing. Exposed to QTP Tool. Academic project – M.Tech [b]TITLE [/b]: Analyzing the performance of the Transceiver in Reconfigurable Platforms [b]Duration [/b]: 4 months [b]Software Requirements [/b]: XILINX, MATLAB [b]Objective [/b]: Analyzing the Transceiver performance and applicable in Software Defined Radio Platforms. [b]Description [/b]: Software defined radio (SDR) is an important element of wireless technology and widely used in the telecommunication field. To determine the digital hardware composition of a software radio is a key design step in its creation. Hybrid GPP/DSP/FPGA architecture is an available solution for software defined radio technology. This project presents the Implementation of BPSK Modem with a data rate of 2.4 Mbps message signal with 2.4 MHz and carrier signal with 400 MHz modulated by using a Mixer. BPSK Modem has two main blocks viz., the Carrier Recovery Block and Demodulator Block. The Carrier Recovery was designed by using Costas loop. Costas loop Consists of Mixer, Loop Filter and Numerical Controlled Oscillator (NCO). The Symbol Demodulator accepts digital data input from modulator and Timing Recovery using Early-Late gate Algorithm. Further it performs “Raised cosine filter” with a desired Roll-off factor (0.20). The outputs of Raised cosine filter are applied to Automatic Gain Control, to get the desired outputs which are implemented in FPGA. The project is implemented by using VHDL Simulation tools. To verify the functionality and synthesis Xilinx ISE 9.2I Tools were used. Academic project – B.Tech [b]ORGANIZATION [/b]: DRDL – HYDERABAD [b]TITLE [/b]: Design and Development of Universal Signal Conditioner for Calibration system. [b]Duration [/b]: 4 months [b]Objective [/b]: Design and Development of suitable Hardware and Software for Universal Signal Conditioner to evaluate its performance & characteristics. [b]Description [/b]: Rocket engines based on different propulsion systems are widely used in satellite launching and other flight vehicles. Before the rocket engines are used in actual flights, they are tested in static conditions to evaluate the performance. The performance of the rocket motor can be evaluated by measuring certain parameters like pressure, thrust and displacement. These parameters are measured by pressure transducers, load cells and draw wire sensors respectively. [b]Universal Signal conditioner is aimed to extract and enhance the pressure, thrust, displacement and angle transducers output to a recordable level. The design of signal conditioner is divided into two major functional areas [/b]: Excitation source and Signal processing circuit. Excitation source An 18V AC/750mA transformer and the bridge rectifier configuration are used to meet the excitation voltage and current requirement. The filter capacitance is designed to filter the low frequency ripples less than 100Hz. Software for Universal Signal Conditioner The Calibration Software is developed in ‘C’ Programming Language. The software helps in the calculation of calibration constants of various transducers like Pressure, Displacement, Load Cell. The software also enables the user to manipulate various calibration constants like Sensitivity, Linearity, Hysteresis and Repeatability. Academic details - M.Tech in VLSI Design from SATHYABAMA UNIVERSITY, Chennai, 2010 with an aggregate of 8.4 (C.G.P.A). - B.Tech in Electronics and Communication from Syed Hashim College of Science and Technology, affiliated to JNTU, Hyderabad, 2008 with an aggregate of 59%. - Intermediate from Sri Chaitanya College, Hyderabad under Board of Intermediate Education during 2002-2004 with an aggregate of 66%. - S.S.C from Priyadarsini high School, pithapuram during 2001-2002 with an aggregate of 69%. Achievements - Actively Participated in college and school level DEBATE and ESSAY writing. - Captain of my school and college cricket team. Key strengths - Good communication skills. - Adaptability to any situation. - Ability to work as an individual or in a group. Declaration I hereby declare that all information provided above is true to the best of my knowledge. [b]Place [/b]: Hyderabad [b]Date [/b]: (V.SRICHARAN) ------------------------------------------------------- [b]More Information about this submission and submitter [/b]:- ___________________________________________________ [b]Submission ID [/b]: 4213157 [b]Date & Time [/b]: 5th Jun 2011 9:50 AM (UTC) [b]IP Address [/b]: 117.195.245.112 Browser Info : Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727) Predicted Country : India[/QUOTE]
